LTM4676A_15 Datasheet, PDF (14/130 Pages) Linear Technology – Dual 13A or Single 26A Module Regulator with Digital Power System Management

LTM4676A
Pin Functions
1.000V)—or, optionally, may be set by configuration
resistors; see V_OUT1CFG, V_TRIM1CFG and the Applications
Information section.
SGND (F7-8, G7-8): Channel 1 Negative Voltage Sense
Input. See V_OSNS1. Additionally, SGND is the signal ground
return path of the LTM4676A. If desired, one may place a
test point on one of the four SGND pins and measure its
impedance to GND on one’s hardware (e.g., motherboard,
during ICT post-assembly process) to provide a means
of verifying the integrity of the feedback signal connec-
tion between the other three SGND pins and GND (V_OUT1
power return). SGND is not electrically connected to GND
internal to the LTM4676A. Connect SGND to GND local
to the LTM4676A.
V_ORB1 (J9): Channel 1 Positive Readback Pin. Shorted to
V_OSNS1 internal to the LTM4676A. At one’s option, place
a test point on this node and measure its impedance to
V_OUT1 on one’s hardware (e.g., motherboard, during ICT
post-assembly process) to provide a means of verifying
the integrity of the feedback signal connection between
V_OUT1 and V_OSNS1.
V_IN0 (A11-12, B11-12, C11-12, D11-12, E12): Positive
Power Input to Channel 0 Switching Stage. Provide suf-
ficient decoupling capacitance in the form of multilayer
ceramic capacitors (MLCCs) and low ESR electrolytic (or
equivalent) to handle reflected input current ripple from the
step-down switching stage. MLCCs should be placed as
close to the LTM4676A as physically possible. See Layout
Recommendations in the Applications Information section.
V_IN1 (H12, J11-12, K11-12, L11-12, M11-12): Positive
Power Input to Channel 1 Switching Stage. Provide suf-
ficient decoupling capacitance in the form of MLCCs and
low ESR electrolytic (or equivalent) to handle reflected
input current ripple from the step-down switching stage.
MLCCs should be placed as close to the LTM4676A as
physically possible. See Layout Recommendations in the
Applications Information section.
SW₀ (B10): Switching Node of Channel 0 Step-Down
Converter Stage. Used for test purposes or EMI-snubbing
heavier than that supported by SNUB₀. May be routed a
short distance to a local test point to monitor switching
action of Channel 0, if desired, but do not route near any
sensitive signals; otherwise, leave electrically isolated
(open).
SW₁ (L10): Switching Node of Channel 1 Step-Down
Converter Stage. Used for test purposes or EMI-snubbing
heavier than that supported by SNUB₁. May be routed a
short distance to a local test point to monitor switching
action of Channel 1, if desired, but do not route near any
sensitive signals; otherwise, leave open.
SNUB₀ (A5): Access to Channel 0 Switching Stage Snubber
Capacitor. Connecting an optional resistor from SNUB₀ to
GND can reduce radiated EMI, with only a minor penalty
towards power conversion efficiency. See the Applications
Information section. Pin should otherwise be left open.
SNUB₁ (M5): Access to Channel 1 Switching Stage Snubber
Capacitor. Connecting an optional resistor from SNUB₀ to
GND can reduce radiated EMI, with only a minor penalty
towards power conversion efficiency. See the Applications
Information section. Pin should otherwise be left open.
SV_IN (F11-12): Input Supply for LTM4676A’s Internal
Control IC. In most applications, SV_IN connects to V_IN0
and/or V_IN1, in which case no external decoupling beyond
that already allocated for V_IN0/V_IN1 is required. If SV_IN is
operated from an auxiliary supply separate from V_IN0/V_IN1,
decouple this pin to GND with a capacitor (0.1μF to 1μF).
INTV_CC (F9, G9): Internal Regulator, 5V Output. When
operating the LTM4676A from 5.75V ≤ SV_IN ≤ 17V, an LDO
generates INTV_CC from SV_IN to bias internal control circuits
and the MOSFET drivers of the LTM4676A. No external
decoupling is required. INTV_CC is regulated regardless of
the RUN_n pin state. When operating the LTM4676A with
4.5V ≤ SV_IN < 5.75V, INTV_CC must be electrically shorted
to SV_IN.
V_DD33 (J7): Internally Generated 3.3V Power Supply
Output Pin. This pin should only be used to provide ex-
ternal current for the pull-up resistors required for GPIO_n,
SHARE_CLK, and SYNC, and may be used to provide
external current for pull-up resistors on RUN_n, SDA, SCL
and ALERT. No external decoupling is required.
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