LTC3556 Datasheet, PDF (33/36 Pages) Linear Technology – High Effi ciency USB Power Manager with Dual Buck and Buck-Boost DC/DCs

LTC3556
APPLICATIONS INFORMATION
The GATE pin for the external ideal diode controller has
extremely limited drive current. Care must be taken to
minimize leakage to adjacent PC board traces. 100nA of
leakage from this pin will introduce an offset to the 15mV
ideal diode of approximately 10mV. To minimize leakage,
the trace can be guarded on the PC board by surrounding
it with V_OUT connected metal, which should generally be
less that one volt higher than GATE.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3556.
1. Are the capacitors at V_BUS, V_IN1, V_IN2 and V_IN3 as close
as possible to the LTC3556? These capacitors provide
the AC current to the internal power MOSFETs and their
drivers. Minimizing inductance from these capacitors
to the LTC3556 is a top priority.
2. Are C_OUT and L1 closely connected? The (–) plate of C_OUT
returns current to the GND plane, and then back to C_IN.
3. Keep sensitive components away from the SW pins.
Battery Charger Stability Considerations
The LTC3556’s battery charger contains both a constant-
voltage and a constant-current control loop. The constant-
voltage loop is stable without any compensation when a
battery is connected with low impedance leads. Excessive
lead length, however, may add enough series inductance
to require a bypass capacitor of at least 1μF from BAT to
GND. Furthermore, when the battery is disconnected, a
100μF OSCON B6 capacitor in series with a 0Ω jumper
from BAT to GND is required to keep ripple voltage low.
High value, low ESR multilayer ceramic chip capacitors
reduce the constant-voltage loop phase margin, possibly
resulting in instability. Ceramic capacitors up to 22μF may
be used in parallel with a battery, but larger ceramics should
be decoupled with 0.2Ω to 1Ω of series resistance.
In constant-current mode, the PROG pin is in the feed-
back loop rather than the battery voltage. Because of the
additional pole created by any PROG pin capacitance,
capacitance on this pin must be kept to a minimum. With
no additional capacitance on the PROG pin, the battery
charger is stable with program resistor values as high
as 25k. However, additional capacitance on this node
reduces the maximum allowed program resistor. The pole
frequency at the PROG pin should be kept above 100kHz.
Therefore, if the PROG pin has a parasitic capacitance,
C_PROG, the following equation should be used to calculate
the maximum resistance value for R_PROG:
R_PROG
≤
2π
•
1
100kHz
•
C_PROG
3556 F09
Figure 9. Higher Frequency Ground Currents Follow Their Incident Path.
Slices in the Ground Plane Cause High Voltage and Increased Emissions
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