LTC3733 Datasheet, PDF (3/32 Pages) Linear Technology – 3-Phase, Buck Controllers for AMD CPUs

LTC3733/LTC3733-1
ELECTRICAL CHARACTERISTICS The q denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T_A = 25°C. V_CC = V_RUN = V_SS = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
V_LOADREG
V_REFLNREG
g_m
g_mOL
V_FCB
I_FCB
V_BINHIBIT
UVR
I_Q
V_RUN
I_SS
V_SSARM
Output Voltage Load Regulation
Output Voltage Line Regulation
Transconductance Amplifier g_m
Transconductance Amplifier GBW
Forced Continuous Threshold
FCB Bias Current
Burst Inhibit Threshold
Undervoltage SS Reset
Input DC Supply Current
Normal Mode
Shutdown
RUN Pin ON Threshold
Soft-Start Charge Current
SS Pin Arming Threshold
(Note 3)
Measured in Servo Loop, ∆I_TH Voltage = 1.2V to 0.7V
Measured in Servo Loop, ∆I_TH Voltage = 1.2V to 2V
V_CC = 4.5V to 7V
I_TH = 1.2V, Sink/Source 25µA (Note 3)
I_TH = 1.2V, (g_m • Z_L, Z_L = Series 1k-100kΩ-1nF)
V_FCB = 0.65V
Measured at FCB pin
V_CC Lowered Until the SS Pin is Pulled Low
(Note 4)
V_CC = 5V
V_RUN = 0V, VID0 to VID4 Open
V_RUN, Ramping Positive
V_SS = 1.9V
V_SS, Ramping Positive Until Short-Circuit
Latch-Off is Armed
q
0.1
0.5
%
q
–0.1 –0.5
%
0.03
%/V
2.5
3.05
3.6 mmho
1.5
MHz
q 0.58 0.60 0.62
V
0.2
0.7
µA
V_CC – 1.5 V_CC – 0.7 V_CC – 0.3
V
3.3
3.8
4.5
V
2.5
mA
20
100
µA
1
1.5
1.9
V
–0.8 –1.5 –2.5
µA
3.8
4.5
V
V_SSLO
I_SCL
I_SDLHO
I_SENSE
SS Pin Latch-Off Threshold
SS Discharge Current
Shutdown Latch Disable Current
SENSE Pins Source Current
V_SS, Ramping Negative
Soft-Short Condition V_EAIN = 0.375V, V_SS = 4.5V
V_EAIN = 0.375V, V_SS = 4.5V
SENSE1⁺, SENSE1^–, SENSE2⁺, SENSE2^–,
SENSE3⁺, SENSE3^– All Equal 1.2V; Current at Each Pin
3.3
V
–5
– 1.5
µA
1.5
5
µA
13
20
µA
DF_MAX
TG t_R,t_F
BG t_R, t_F
TG/BG t_1D
Maximum Duty Factor
In Dropout
Top Gate Rise Time
Top Gate Fall Time
C_LOAD = 3300pF
C_LOAD = 3300pF
Bottom Gate Rise Time
Bottom Gate Fall Time
C_LOAD = 3300pF
C_LOAD = 3300pF
Top Gate Off to Bottom Gate On Delay All Controllers, C_LOAD = 3300pF Each Driver
Synchronous Switch-On Delay Time
95
98.5
%
30
90
ns
40
90
ns
30
90
ns
20
90
ns
60
ns
BG/TG t_2D
Bottom Gate Off to Top Gate On Delay All Controllers, C_LOAD = 3300pF Each Driver
Top Switch-On Delay Time
60
ns
t_ON(MIN)
Minimum On-Time
VID Parameters
Tested with a Square Wave (Note 5)
120
ns
VID_IL
VID_IH
VID_PULLUP
Maximum Low Level Input Voltage
Minimum High Level Input Voltage
VID0 to VID4 Internal Pull-Up
Resistance
0.8
V
2
V
150
kΩ
ATTEN_ERR VID0 to VID4
Power Good Output Indication
(Note 6)
q –0.25
0.25
%
V_PGL
I_PGOOD
V_PGTHNEG
V_PGTHPOS
t_PGBLNK
PGOOD Voltage Output Low
PGOOD Output Leakage
PGOOD Trip Thesholds
V_DIFFOUT Ramping Negative
V_DIFFOUT Ramping Positive
Power Good Blanking
I_PGOOD = 2mA
V_PGOOD = 5V
V_DIFFOUT with Respect to Set Output Voltage,
VID Code = 10011
PGOOD Goes Low After V_UVDLY Delay
After VID Changes Outside PGOOD Window
0.1
0.3
V
±1
µA
–7
–10 –14
%
7
10
14
%
120
µs
3733f
3