LTC3733 Datasheet, PDF (16/32 Pages) Linear Technology – 3-Phase, Buck Controllers for AMD CPUs

LTC3733/LTC3733-1
APPLICATIO S I FOR ATIO
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The Schottky diodes, D1 to D3 shown in Figure 1 conduct
during the dead time between the conduction of the two
large power MOSFETs. This prevents the body diode of the
bottom MOSFET from turning on, storing charge during
the dead time and requiring a reverse recovery period
which could cost as much as several percent in efficiency.
A 2A to 8A Schottky is generally a good compromise for
both regions of operation due to the relatively small
average current. Larger diodes result in additional transi-
tion losses due to their larger junction capacitance.
C_IN and C_OUT Selection
Input capacitance ESR requirements and efficiency losses
are reduced substantially in a multiphase architecture
because the peak current drawn from the input capacitor
is effectively divided by the number of phases used and
power loss is proportional to the RMS current squared. A
3-stage, single output voltage implementation can reduce
input path power loss by 90%.
In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle V_OUT/V_IN.
A low ESR input capacitor sized for the maximum RMS
current must be used. The details of a close form equation
can be found in Application Note 77. Figure 6 shows the
input capacitor ripple current for different phase configu-
rations with the output voltage fixed and input voltage
varied. The input ripple current is normalized against the
DC output current. The graph can be used in place of
tedious calculations. The minimum input ripple current
can be achieved when the product of phase number and
output voltage, N(V_OUT), is approximately equal to the
input voltage V_IN or:
V_{OUT =} k _{where k = 1, 2, ..., N – 1}
V_IN N
So the phase number can be chosen to minimize the input
capacitor size for the given input and output voltages.
In the graph of Figure 6, the local maximum input RMS
capacitor currents are reached when:
V_{OUT =} 2k – 1 _{where k = 1, 2, ..., N}
V_IN
N
These worst-case conditions are commonly used for de-
sign because even significant deviations do not offer much
relief. Note that capacitor manufacturer’s ripple current
ratings are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than re-
quired. Several capacitors may also be paralleled to meet
size or height requirements in the design. Always consult
the capacitor manufacturer if there is any question.
The Figure 6 graph shows that the peak RMS input current
is reduced linearly, inversely proportional to the number N
of stages used. It is important to note that the efficiency
loss is proportional to the input RMS current squared and
therefore a 3-stage implementation results in 90% less
power loss when compared to a single phase design.
Battery/input protection fuse resistance (if used), PC
0.6
0.5
1-PHASE
0.4
2-PHASE
3-PHASE
0.3
4-PHASE
6-PHASE
0.2
0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
DUTY FACTOR (V_OUT/V_IN)
3733 F06
Figure 6. Normalized Input RMS Ripple Current
vs Duty Factor for One to Six Output Stages
3733f
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