LTC3733 Datasheet, PDF (21/32 Pages) Linear Technology – 3-Phase, Buck Controllers for AMD CPUs

LTC3733/LTC3733-1
APPLICATIO S I FOR ATIO
The emitter of Q1 will hold up the EAIN pin to a voltage in
the absence of V_OUT that will prevent the internal sensing
circuitry from reducing the peak output current. Remov-
ing the function in this manner eliminates the external
MOSFET’s protective feature under short-circuit condi-
tions. This technique will also prevent the short-circuit
latchoff function from turning off the part during a short-
circuit event and the output current will only be limited to
N • 75mV/R_SENSE.
Undervoltage Reset
In the event that the input power source to the IC (V_CC)
drops below 4V, the SS capacitor will be discharged to
ground and the controller will be shut down. When V_CC
rises above 4V, the SS capacitor will be allowed to re-
charge and initiate another soft-start turn-on attempt. This
may be useful in applications that switch between two
supplies that are not diode connected, but note that this
cannot make up for the resultant interruption of the
regulated output.
Phase-Locked Loop and
Frequency Synchronization (LTC3733-1)
The IC has a phase-locked loop comprised of an internal
voltage controlled oscillator and phase detector. This
allows the top MOSFET of output stage 1’s turn-on to be
locked to the rising edge of an external source. The
frequency range of the voltage controlled oscillator is
±50% around the center frequency f_O. A voltage applied to
the PLLFLTR pin of 1.2V corresponds to a frequency of
approximately 350kHz. The nominal operating frequency
range of the IC is 210kHz to 530kHz.
The phase detector used is an edge sensitive digital type
that provides zero degrees phase shift between the
external and internal oscillators. This type of phase
detector will not lock the internal oscillator to harmonics
of the input frequency. The PLL hold-in range, ∆f_H, is
equal to the capture range, ∆f_C:
∆f_H = ∆f_C = ±0.5 f_O
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter components on the PLLFLTR pin. A simplified block
diagram is shown in Figure 9.
If the external frequency (f_PLLIN) is greater than the oscil-
lator frequency, f_OSC, current is sourced continuously,
pulling up the PLLFLTR pin. When the external frequency
is less than f_OSC, current is sunk continuously, pulling
down the PLLFLTR pin. If the external and internal fre-
quencies are the same, but exhibit a phase difference, the
current sources turn on for an amount of time correspond-
ing to the phase difference. Thus, the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point, the phase comparator output is
open and the filter capacitor C_LP holds the voltage. The IC
PLLIN pin must be driven from a low impedance source
such as a logic gate located close to the pin. When using
multiple ICs for a phase-locked system, the PLLFLTR pin
of the master oscillator should be biased at a voltage that
will guarantee the slave oscillator(s) ability to lock onto the
master’s frequency. A voltage of 1.7V or below applied to
the master oscillator’s PLLFLTR pin is recommended in
order to meet this requirement. The resultant operating
frequency will be approximately 500kHz for 1.7V.
PHASE
2.4V
DETECTOR/
OSCILLATOR
EXTERNAL
OSC
PLLIN
(LTC3733-1
ONLY)
DIGITAL
PHASE/
FREQUENCY
50k
DETECTOR
R_LP
10k
C_LP
PLLFLTR
OSC
3733 F09
Figure 9. Phase-Locked Loop Block Diagram
3733f
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