LTC3407A Datasheet, PDF (3/16 Pages) Linear Technology – Dual Synchronous 600mA, 1.5MHz Step-Down DC/DC Regulator

LTC3407A
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T_A = 25°C. V_IN = 3.6V, unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP MAX
UNITS
ΔV_{LOAD REG}
I_S
Output Voltage Load Regulation
Input DC Supply Current
Active Mode
Sleep Mode
Shutdown
MODE/SYNC = 0V (Note 3)
(Note 4)
V_FB1 = V_FB2 = 0.5V
V_FB1 = V_FB2 = 0.63V, MODE/SYNC = 3.6V
RUN = 0V, V_IN = 5.5V, MODE/SYNC = 0V
0.5
%
600 800
μA
40
60
μA
0.1
1
μA
f_OSC
Oscillator Frequency
V_FBX = 0.6V
●
1.2
1.5
1.8
MHz
f_SYNC
Synchronization Frequency
1.5
MHz
I_LIM
Peak Switch Current Limit
V_IN = 3V, V_FBX = 0.5V, Duty Cycle <35%
0.75
1
1.25
A
R_DS(ON)
Top Switch On-Resistance
Bottom Switch On-Resistance
(Note 6)
(Note 6)
0.35 0.45
Ω
0.30 0.45
Ω
I_SW(LKG)
Switch Leakage Current
V_IN = 5V, V_RUN = 0V, V_FBX = 0V
0.01
1
μA
POR
Power-On Reset Threshold
V_FBX Ramping Up, MODE/SYNC = 0V
V_FBX Ramping Down, MODE/SYNC = 0V
Power-On Reset On-Resistance
8.5
%
–8.5
%
100 200
Ω
Power-On Reset Delay
65,536
Cycles
V_RUN
RUN/SS Threshold Low
RUN/SS Threshold High
●
0.3
1
1.5
V
●
2
V
I_RUN
V_MODE
RUN/SS Leakage Current
MODE Threshold Low
●
0.01
1
μA
0
0.5
V
MODE Threshold High
V_IN – 0.5
V_IN
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3407AE is guaranteed to meet specified performance
from 0°C to 85°C. Specifications over the –40°C and 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3407AI is guaranteed over the full
–40°C to 125°C temperature range.
Note 3: The LTC3407A is tested in a proprietary test mode that connects
V_FB to the output of the error amplifier.
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: T_J is calculated from the ambient T_A and power dissipation P_D
according to the following formula: T_J = T_A + (P_D • θ_JA).
Note 6: The DFN switch on-resistance is guaranteed by correlation to
wafer level measurements.
TYPICAL PERFORMANCE CHARACTERISTICS
Burst Mode Operation
Pulse Skipping Mode
SW
5V/DIV
V_OUT
50mV/DIV
SW
5V/DIV
V_OUT
10mV/DIV
I_L
200mA/DIV
V_IN = 3.6V
2μs/DIV
V_OUT = 1.8V
I_LOAD = 50mA
CIRCUIT OF FIGURE 3
3407 G01
I_L
100mA/DIV
V_IN = 3.6V
1μs/DIV
V_OUT = 1.8V
I_LOAD = 50mA
CIRCUIT OF FIGURE 3
3407 G02
3407afa
3