LTC3555 Datasheet, PDF (29/32 Pages) Linear Technology – High Effi ciency USB Power Manager + Triple Step-Down DC/DC

APPLICATIONS INFORMATION
LTC3555/LTC3555-X
5V USB
INPUT _{USB CABLE}
MP1
Si2333
C1
100nF
R1
40k
V_BUS
C2
10μF
LTC3555/
LTC3555-X
GND
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Figure 6. USB Soft Connect Circuit
the IC and all of its external high frequency components.
High frequency currents, such as the V_BUS, V_IN1, V_IN2
and V_IN3 currents on the LTC3555 family, tend to find
their way along the ground plane in a myriad of paths
ranging from directly back to a mirror path beneath the
incident path on the top of the board. If there are slits or
cuts in the ground plane due to other traces on that layer,
the current will be forced to go around the slits. If high
frequency currents are not allowed to flow back through
their natural least-area path, excessive voltage will build
up and radiated emissions will occur. There should be a
group of vias under the grounded backside of the pack-
age leading directly down to an internal ground plane. To
minimize parasitic inductance, the ground plane should
be on the second layer of the PC board.
The GATE pin for the external ideal diode controller has
extremely limited drive current. Care must be taken to
minimize leakage to adjacent PC board traces. 100nA of
leakage from this pin will introduce an offset to the 15mV
ideal diode of approximately 10mV. To minimize leakage,
the trace can be guarded on the PC board by surrounding
it with V_OUT connected metal, which should generally be
less that one volt higher than GATE.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3555 family.
1. Are the capacitors at V_BUS, V_IN1, V_IN2 and V_IN3 as close
as possible to the LTC3555? These capacitors provide
the AC current to the internal power MOSFETs and their
drivers. Minimizing inductance from these capacitors
to the LTC3555 is a top priority.
2. Are C_OUT and L1 closely connected? The (–) plate of
C_OUT returns current to the GND plane.
3. Keep sensitive components away from the SW pins.
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Figure 7. Higher Frequency Ground Currents Follow Their
Incident Path. Slices in the Ground Plane Cause High Voltage
and Increased Emissions
Battery Charger Stability Considerations
The LTC3555 family’s battery charger contains both a
constant-voltage and a constant-current control loop.
The constant-voltage loop is stable without any compen-
sation when a battery is connected with low impedance
leads. Excessive lead length, however, may add enough
series inductance to require a bypass capacitor of at least
1μF from BAT to GND. Furthermore, when the battery is
disconnected, a 100μF MLCC capacitor in series with a
0.3Ω resistor from BAT to GND is required to prevent
oscillation.
High value, low ESR multilayer ceramic chip capacitors
reduce the constant-voltage loop phase margin, possibly
resulting in instability. Ceramic capacitors up to 22μF may
be used in parallel with a battery, but larger ceramics should
be decoupled with 0.2Ω to 1Ω of series resistance.
In constant-current mode, the PROG pin is in the feed-
back loop rather than the battery voltage. Because of the
additional pole created by any PROG pin capacitance,
capacitance on this pin must be kept to a minimum. With
no additional capacitance on the PROG pin, the battery
charger is stable with program resistor values as high
as 25k. However, additional capacitance on this node
reduces the maximum allowed program resistor. The pole
frequency at the PROG pin should be kept above 100kHz.
Therefore, if the PROG pin has a parasitic capacitance,
C_PROG, the following equation should be used to calculate
the maximum resistance value for R_PROG:
R_PROG
≤
2π
•
1
100kHz
•
C_PROG
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