LTC3576-1_15 Datasheet, PDF (28/48 Pages) Linear Technology – Switching Power Manager with USB On-the-Go Triple Step-Down DC/DCs

LTC3576/LTC3576-1
OPERATION
Byte Format
Each byte sent to the LTC3576/LTC3576-1 must be eight bits
long followed by an extra clock cycle for the acknowledge
bit. The data should be sent to the LTC3576/LTC3576-1
with the most significant bit (MSB) first.
Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. An acknowledge (active low)
generated by the slave (LTC3576/LTC3576-1) lets the mas-
ter know that the latest byte of information was received.
The acknowledge related clock pulse is generated by the
master. The master releases the SDA line (HIGH) during
the acknowledge clock cycle. The slave-receiver must pull
down the SDA line during the acknowledge clock pulse
so that it remains a stable LOW during the HIGH period
of this clock pulse.
Slave Address
The address byte consists of the 7-bit address and the
read/write (R/W) bit. The LTC3576/LTC3576-1 respond to
only one 7-bit address which has been factory programmed
to 0001001. The R/W bit is the least significant bit of the
address byte. It must be 0 for the LTC3576/LTC3576-1 to
recognize the address since they are write only devices.
Thus the address byte is 0x12. If the correct seven bit ad-
dress is given but the R/W bit is 1, the LTC3576/LTC3576-1
will not respond.
Sub-Addressed Writing
The LTC3576/LTC3576-1 have four command registers
for control input. They are accessed by the I²C port via a
sub-addressed writing system.
Each write to the LTC3576/LTC3576-1 consists of three
bytes. The first byte is always the LTC3576/LTC3576-1’s
write address. The second byte represents the LTC3576/
LTC3576-1’s sub-address. The sub-address acts as
pointer to direct the subsequent data byte within the
LTC3576/LTC3576-1. The third byte consists of the data to
be written to the location pointed to by the sub-address.
The LTC3576/LTC3576-1 contain four sub-addresses at
locations 0x00, 0x01, 0x02 and 0x03.
Bus Write Operation
The master initiates communication with the LTC3576/
LTC3576-1 with a START condition and a 7-bit address
followed by the R/W bit = 0. If the address matches that
of the LTC3576/LTC3576-1, the LTC3576/LTC3576-1 return
an acknowledge. The master should then deliver the sub-
address. Again the LTC3576/LTC3576-1 acknowledge and
the cycle is repeated for the data byte. The data byte is
transferred to an internal holding latch upon the return of its
acknowledge by the LTC3576/LTC3576-1. This procedure
must be repeated for each sub-address that requires new
data. After one or more data bytes have been transferred
to the LTC3576/LTC3576-1, the master may terminate the
communication with a STOP condition. Alternatively, a
repeated START condition can be initiated by the master
and another chip on the I²C bus can be addressed. This
cycle can continue indefinitely and the LTC3576/LTC3576-1
remembers the last input of valid data that it received.
Once all chips on the bus have been addressed and sent
valid data, a global STOP condition can be sent and the
LTC3576/LTC3576-1 will update their command latches
with the data that they have received.
In certain circumstances the data on the I²C bus may be-
come corrupted. In these cases, the LTC3576/LTC3576-1
respond appropriately by preserving only the last set
of complete data that they have received. For example,
assume the LTC3576/LTC3576-1 have been successfully
addressed and are receiving data when a STOP condition
mistakenly occurs. The LTC3576/LTC3576-1 will ignore this
STOP condition and will not respond until a new START
condition, correct address and sub-address, new set of
data and STOP condition are transmitted.
Likewise, with only one exception, if the LTC3576/
LTC3576-1 were previously addressed and sent valid data
but not updated with a STOP, they will respond to any
STOP that appears on the bus, independent of the num-
ber of repeated STARTs that have occurred. If a repeated
START is given and the LTC3576/LTC3576-1 successfully
acknowledge their address and sub-address, they will not
respond to a STOP until a full byte of the new data has
been received and acknowledged.
3576fb
28