LTC3556_15 Datasheet, PDF (28/36 Pages) Linear Technology – High Effi ciency USB Power Manager with Dual Buck and Buck-Boost DC/DCs

LTC3556
APPLICATIONS INFORMATION
Closing the Feedback Loop
The LTC3556 incorporates voltage mode PWM control. The
control to output gain varies with operation region (buck,
boost, buck-boost), but is usually no greater than 20. The
output filter exhibits a double-pole response given by:
f_{FILTER_POLE} = _{2 • π •}
1
L • C_OUT
Hz
where C_OUT is the output filter capacitor.
The output filter zero is given by:
f_{FILTER _ ZERO} =
1
2 • π • R_ESR • C_OUT
Hz
where R_ESR is the capacitor equivalent series resistance.
A troublesome feature in boost mode is the right-half plane
zero (RHP), and is given by:
f_RHPZ
=
V_IN2
2 • π • I_OUT • L • V_OUT
Hz
The loop gain is typically rolled off before the RHP zero
frequency.
A simple Type I compensation network (as shown in
Figure 5) can be incorporated to stabilize the loop but
at the cost of reduced bandwidth and slower transient
response. To ensure proper phase margin, the loop must
cross unity-gain a decade before the LC double pole.
The unity-gain frequency of the error amplifier with the
Type I compensation is given by:
f_UG
=
2
•
π
•
1
R1•
CP1
Hz
Most applications demand an improved transient response
to allow a smaller output filter capacitor. To achieve a higher
bandwidth, Type III compensation is required. Two zeros
are required to compensate for the double-pole response.
Type III compensation also reduces any V_OUT3 overshoot
at start-up.
The compensation network depicted in Figure 6 yields the
transfer function:
V_{C3 =}
1
V_OUT3 R1(C1+ C2)
• ^{(1+ sR2C2) [1+ s(R1+ R3)C3]}
s ⎡⎣1+ sR2(C1|| C2)⎤⎦ (1+ sR3C3)
A Type III compensation network attempts to introduce
a phase bump at a higher frequency than the LC double
pole. This allows the system to cross unity gain after the
LC double pole, and achieve a higher bandwidth. While
attempting to cross over after the LC double pole, the
system must still cross over before the boost right-half
plane zero. If unity gain is not reached sufficiently before
the right-half plane zero, then the –180° of phase lag from
ERROR
AMP
0.8V
FB3
7
V_C3 ^CP1
8
V_OUT3
R1
R2
3556 F05
Figure 5. Error Amplifier with Type I Compensation
V_OUT3
ERROR
AMP
0.8V
FB3
7
V_C3
8
C2
R2
C1
R1
R3
C3
R_FB
3556 F06
Figure 6. Error Amplifier with Type III Compensation
3556f
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