LTC3556_15 Datasheet, PDF (20/36 Pages) Linear Technology – High Effi ciency USB Power Manager with Dual Buck and Buck-Boost DC/DCs

LTC3556
OPERATION
Table 2. I²C Serial Port Mapping (Defaults to 0xFF00 in Reset State or if DV_CC = 0V)
A7 A6 A5 A4 A3 A2 A1 A0
B7
B6
B5
B4
B3
B2
B1
B0
Switching Regulator 1
Voltage (See Table 4)
Switching Regulator 3
Voltage (See Table 4)
Disable Switching Regulator Enable Enable Enable Input Current Limit
Battery Modes (See Table 5) Regulator Regulator Regulator (See Table 3)
Charger
1
2
3
Table 3. USB Current Limit Settings
B1
B0
USB SETTING
0
1
10x Mode (Wall 1A Limit)
1
1
5x Mode (USB 500mA Limit)
0
0
1x Mode (USB 100mA Limit)
1
0
Suspend
Table 4. Switching Regulator Servo Voltage
A7 A6 A5 A4 SWITCHING REGULATOR 1 SERVO VOLTAGE
A3 A2 A1 A0 SWITCHING REGULATOR 3 SERVO VOLTAGE
0000
0.425V
0001
0.450V
0010
0.475V
0011
0.500V
0100
0.525V
0101
0.550V
0110
0.575V
0111
0.600V
1000
0.625V
1001
0.650V
1010
0.675V
1011
0.700V
1100
0.725V
1101
0.750V
1110
0.775V
1111
0.800V
Table 5. Switching Regulator Modes
MODE OF (BUCK) SWITCHING MODE OF (BUCK-BOOST)
B6 B5 REGULATORS 1 AND 2
SWITCHING REGULATOR 3
0 0 Pulse Skip Mode
PWM Mode
1 1 Burst Mode Operation
0 1 Forced Burst Mode Operation Burst Mode Operation
1 0 LDO Mode
Bus Write Operation
The master initiates communication with the LTC3556
with a Start condition and a 7-bit address followed by
the Write Bit R/W = 0. If the address matches that of the
LTC3556, the LTC3556 returns an Acknowledge. The master
should then deliver the most significant data byte. Again
the LTC3556 acknowledges and the cycle is repeated for
a total of one address byte and two data bytes. Each data
byte is transferred to an internal holding latch upon the
return of an Acknowledge. After both data bytes have been
transferred to the LTC3556, the master may terminate the
communication with a Stop condition. Alternatively, a
Repeat-Start condition can be initiated by the master and
another chip on the I²C bus can be addressed. This cycle
can continue indefinitely and the LTC3556 will remember
the last input of valid data that it received. Once all chips on
the bus have been addressed and sent valid data, a global
Stop condition can be sent and the LTC3556 will update its
command latch with the data that it had received.
In certain circumstances the data on the I²C bus may
become corrupted. In these cases the LTC3556 responds
appropriately by preserving only the last set of complete
data that it has received. For example, assume the LTC3556
has been successfully addressed and is receiving data
when a Stop condition mistakenly occurs. The LTC3556
will ignore this stop condition and will not respond until
a new Start condition, correct address, new set of data
and Stop condition are transmitted.
Likewise, with only one exception, if the LTC3556 was
previously addressed and sent valid data but not updated
with a Stop, it will respond to any Stop that appears on
the bus, independent of the number of Repeat-Starts that
have occurred. If a Repeat-Start is given and the LTC3556
successfully acknowledges its address and first byte, it
will not respond to a Stop until both bytes of the new data
have been received and acknowledged.
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