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LTC3857 Datasheet, PDF (27/38 Pages) Linear Technology – Low IQ, Dual, 2-Phase Synchronous Step-Down Controller
LTC3857
Applications Information
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 11. Figure 12 illustrates the current
waveforms present in the various branches of the 2-phase
synchronous regulators operating in the continuous mode.
Check the following in your layout:
1. Are the top N-channel MOSFETs MTOP1 and MTOP2
located within 1cm of each other with a common drain
connection at CIN? Do not attempt to split the input
decoupling for the two channels as it can cause a large
resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of CINTVCC must return to the combined COUT (–) ter-
minals. The path formed by the top N-channel MOSFET,
Schottky diode and the CIN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
3. Do the LTC3857 VFB pins’ resistive dividers connect to
the (+) terminals of COUT? The resistive divider must be
connected between the (+) terminal of COUT and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
TRACK/SS1
ITH1
PGOOD2
VFB1
SENSE1+
PGOOD1
TG1
SENSE1–
SW1
LTC3857
FREQ
BOOST1
PHASMD
BG1
CLKOUT
fIN
PLLIN/MODE
VIN
RUN1
RUN2
SGND
SENSE2–
PGND
EXTVCC
INTVCC
SENSE2+
BG2
VFB2
BOOST2
ITH2
SW2
TG2
TRACK/SS2
ILIM
RPU2
VPULL-UP
PGOOD2
RPU1
VPULL-UP
PGOOD1
L1
RSENSE
CB1
M1
M2
D1
CINTVCC
CB2
RIN
CVIN
1µF
CERAMIC
+
VIN
CIN
1µF
CERAMIC
M3
M4
COUT1
+
+
COUT2
D2
RSENSE
L2
VOUT1
GND
VOUT2
Figure 11. Recommended Printed Circuit Layout Diagram
3857 F11
3857fa
27