LTC3857 Datasheet, PDF (23/38 Pages) Linear Technology – Low IQ, Dual, 2-Phase Synchronous Step-Down Controller

LTC3857
Applications Information
Phase-Locked Loop and Frequency Synchronization
The LTC3857 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter,
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the top MOSFET of controller 1 to be locked to
the rising edge of an external clock signal applied to the
PLLIN/MODE pin. The turn-on of controller 2’s top MOSFET
is thus 180 degrees out of phase with the external clock.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, f_OSC, then current is sourced
continuously from the phase detector output, pulling
up the VCO input. When the external clock frequency
is less than f_OSC, current is sunk continuously, pulling
down the VCO input. If the external and internal fre-
quencies are the same but exhibit a phase difference,
the current sources turn on for an amount of time
corresponding to the phase difference. The voltage at the
VCO input is adjusted until the phase and frequency of
the internal and external oscillators are identical. At the
stable operating point, the phase detector output is high
impedance and the internal filter capacitor, C_LP , holds the
voltage at the VCO input.
Note that the LTC3857 can only be synchronized to an
external clock whose frequency is within range of the
LTC3857’s internal VCO, which is nominally 55kHz to 1MHz.
This is guaranteed to be between 75kHz and 850kHz.
Typically, the external clock (on the PLLIN/MODE pin)
input high threshold is 1.6V, while the input low threshold
is 1.1V.
Rapid phase locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired
synchronization frequency. The VCO’s input voltage is
prebiased at a frequency corresponding to the frequency
set by the FREQ pin. Once prebiased, the PLL only needs
to adjust the frequency slightly to achieve phase lock
1000
900
800
700
600
500
400
300
200
100
0
15 25 35 45 55 65 75 85 95 105 115 125
FREQ PIN RESISTOR (kΩ)
3857 F10
Figure 10. Relationship Between Oscillator Frequency
and Resistor Value at the FREQ Pin
and synchronization. Although it is not required that the
free-running frequency be near external clock frequency,
doing so will prevent the operating frequency from passing
through a large range of frequencies as the PLL locks.
Table 2 summarizes the different states in which the FREQ
pin can be used.
Table 2
FREQ PIN
0V
INTV_CC
Resistor
Any of the Above
PLLIN/MODE PIN
DC Voltage
DC Voltage
DC Voltage
External Clock
FREQUENCY
350kHz
535kHz
50kHz-900kHz
Phase–Locked to
External Clock
Minimum On-Time Considerations
Minimum on-time, t_ON(MIN), is the smallest time duration
that the LTC3857 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
( ) ^tON(MIN)
<
V_OUT
V_IN f
3857fa
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