LTC3826_15 Datasheet, PDF (26/36 Pages) Linear Technology – 30A IQ, Dual, 2-Phase Synchronous Step-Down Controller

LTC3826
APPLICATIONS INFORMATION
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C_OUT, causing a rapid drop in V_OUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C_LOAD to C_OUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • C_LOAD. Thus a 10μF capacitor would
require a 250μs rise time, limiting the charging current
to about 200mA.
Design Example
As a design example for one channel, assume V_IN = 12V
(nominal), V_IN = 22V (max), V_OUT = 1.8V, I_MAX = 5A, and
f = 250kHz.
The inductance value is chosen first based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLLPF
pin to GND, generating 250kHz operation. The minimum
inductance for 30% ripple current is:

I_L
=
V_OUT
(f)(L)

¹

–
V_OUT
V_IN



A 4.7μH inductor will produce 23% ripple current and a
3.3μH will result in 33%. The peak inductor current will
be the maximum DC value plus one half the ripple cur-
rent, or 5.84A, for the 3.3μH value. Increasing the ripple
current will also help ensure that the minimum on-time
of 230ns is not violated. The minimum on-time occurs at
maximum V_IN:
t_ON(MIN)
=
V_OUT
V_IN(MAX)f
=
1.8V
22V(250kHz)
=
327ns
The R_SENSE resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
R_SENSE


80mV
5.84A

0.012
Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.
The power dissipation on the top side MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: R_DS(ON) = 0.035Ω/0.022Ω, C_MILLER = 215pF. At
maximum input voltage with T(estimated) = 50°C:
P_MAIN
=
1.8V
22V
(⁵)²
₁₊
(0.005)(50°C
–
25°C)^
•
(^0.035
)
+
(^22V)²


5A
2
^(4
)
(^215p
F₎
•

5
1
 2.3
+
21.3^(300kHz)
=
332mW
A short-circuit to ground will result in a folded back cur-
rent of:
I_SC
=
25mV
0.01

–
21^
1 2 0n s ₍2 2V ₎
3.3μH


=
2.1A
with a typical value of R_DS(ON) and δ = (0.005/°C)(20) = 0.1.
The resulting power dissipated in the bottom MOSFET is:
P_SYNC
=
2
2V – 1.
22V
8V
(^2.1A
)²
(^1.
125₎
(^0.0
22
₎
= 100mW
which is less than under full-load conditions.
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