LTC3826_15 Datasheet, PDF (23/36 Pages) Linear Technology – 30A IQ, Dual, 2-Phase Synchronous Step-Down Controller

LTC3826
APPLICATIONS INFORMATION
to PLLIN/MODE, is shown in Figure 9 and specified in the
Electrical Characteristics table. Note that the LTC3826 can
only be synchronized to an external clock whose frequency
is within range of the LTC3826’s internal VCO, which is
nominally 115kHz to 800kHz. This is guaranteed to be
between 140kHz and 650kHz. A simplified block diagram
is shown in Figure 10.
If the external clock frequency is greater than the internal
oscillator’s frequency, f_OSC, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than f_OSC, current is sunk continuously, pulling down
the PLLLPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLLPF pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor C_LP holds the voltage.
The loop filter components, C_LP and R_LP, smooth out
the current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components C_LP and R_LP determine how fast the loop
acquires lock. Typically R_LP = 10k and C_LP is 2200pF to
0.01μF.
Typically, the external clock (on PLLIN/MODE pin) input high
threshold is 1.6V, while the input low threshold is 1.2V.
Table 2 summarizes the different states in which the
PLLLPF pin can be used.
Table 2
PLLLPF PIN
0V
Floating
INTV_CC
RC Loop Filter
PLLIN/MODE PIN
DC Voltage
DC Voltage
DC Voltage
Clock Signal
FREQUENCY
250kHz
390kHz
530kHz
Phase-Locked to External Clock
Minimum On-Time Considerations
Minimum on-time t_ON(MIN) is the smallest time duration
that the LTC3826 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
t_ON(MIN)
<
V_OUT
V_IN(f)
900
800
700
600
500
400
300
200
100
0
0
0.5
1
1.5
2 2.5
PLLLPF VOLTAGE (V)
3826 F09
Figure 9. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
EXTERNAL
OSCILLATOR
PLLIN/
MODE
DIGITAL
PHASE/
FREQUENCY
DETECTOR
2.4V
R_LP
C_LP
PLLLPF
OSCILLATOR
3826 F10
Figure 10. Phase-Locked Loop Block Diagram
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