LTC3567 Datasheet, PDF (25/28 Pages) Linear Technology – High Effi ciency USB Power Manager Plus 1A Buck-Boost Converter with I2C Control

LTC3567
APPLICATIONS INFORMATION
A simple Type I compensation network (as shown in
Figure 6) can be incorporated to stabilize the loop but at
the cost of reduced bandwidth and slower transient re-
sponse. To ensure proper phase margin, the loop must
cross unity-gain a decade before the LC double pole.
V_OUT1
0.8V
R1
ERROR
AMP
FB1
V_C1 ^CP1
R_FB
3567 F06
Figure 6. Error Amplifier with Type I Compensation
The unity-gain frequency of the error amplifier with the
Type I compensation is given by:
f
UG
=
2
•
π
•
1
R1•
C_P1
Hz
Most applications demand an improved transient response
to allow a smaller output filter capacitor. To achieve a higher
bandwidth, Type III compensation is required. Two zeros
are required to compensate for the double-pole response.
Type III compensation also reduces any V_OUT1 overshoot
seen at start-up.
The compensation network depicted in Figure 7 yields the
transfer function:
V_C1
V_OUT1
=
R1•
1
(C1+
C2)
•
(1+
s
•



sR2C2) • (1+ s(R1+
1+
sR2C1C2
C1+ C2


•
(1+
R3)C3)
sR3C3)
ERROR
AMP
V_OUT1
0.8V
FB1
R3
R1
C3
V_C1
C2
R2
R_FB
C1
3567 F07
Figure 7. Error Amplifier with Type III Compensation
A Type III compensation network attempts to introduce
a phase bump at a higher frequency than the LC double
pole. This allows the system to cross unity gain after the
LC double pole, and achieve a higher bandwidth. While
attempting to cross over after the LC double pole, the
system must still cross over before the boost right-half
plane zero. If unity gain is not reached sufficiently before
the right-half plane zero, then the –180° of phase lag from
the LC double pole combined with the –90° of phase lag
from the right-half plane zero will result in negating the
phase bump of the compensator.
The compensator zeros should be placed either before
or only slightly after the LC double pole such that their
positive phase contributions offset the –180° that occurs
at the filter double pole. If they are placed at too low of a
frequency, they will introduce too much gain to the system
and the crossover frequency will be too high. The two high
frequency poles should be placed such that the system
crosses unity gain during the phase bump introduced
by the zeros and before the boost right-half plane zero
and such that the compensator bandwidth is less than
the bandwidth of the error amp (typically 900kHz). If the
gain of the compensation network is ever greater than
the gain of the error amplifier, then the error amplifier no
longer acts as an ideal op-amp, and another pole will be
introduced at the same point.
Recommended Type III compensation components for a
3.3V output:
R1: 324kΩ
R_FB: 105kΩ
C1: 10pF
R2: 15kΩ
C2: 330pF
R3: 121kΩ
C3: 33pF
C_OUT: 22μF
L_OUT: 2.2μH
Printed Circuit Board Layout Considerations
In order to be able to deliver maximum current under
all conditions, it is critical that the Exposed Pad on the
backside of the LTC3567 package be soldered to the PC
board ground. Failure to make thermal contact between
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