LTC3567 Datasheet, PDF (17/28 Pages) Linear Technology – High Effi ciency USB Power Manager Plus 1A Buck-Boost Converter with I2C Control

LTC3567
OPERATION
to approximately 0°C. The hot and cold comparators each
have approximately 3°C of hysteresis to prevent oscillation
about the trip point. Grounding the NTC pin disables the
NTC charge pausing function.
Thermal Regulation
To optimize charging time, an internal thermal feedback
loop may automatically decrease the programmed charge
current. This will occur if the die temperature rises to
approximately 110°C. Thermal regulation protects the
LTC3567 from excessive temperature due to high power
operation or high ambient thermal conditions and allows
the user to push the limits of the power handling capability
with a given circuit board design without risk of damag-
ing the LTC3567 or external components. The benefit
of the LTC3567 thermal regulation loop is that charge
current can be set according to actual conditions rather
than worst-case conditions with the assurance that the
battery charger will automatically reduce the current in
worst-case conditions.
I²C Interface
The LTC3567 may receive commands from a host (mas-
ter) using the standard I²C 2-wire interface. The Timing
Diagram shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources, such as the LTC1694 I²C accelerator, are
required on these lines. The LTC3567 is a receive-only
(slave) device. The I²C control signals, SDA and SCL are
scaled internally to the DV_CC supply. DV_CC should be con-
nected to the same power supply as the microcontroller
generating the I²C signals.
The I²C port has an undervoltage lockout on the DV_CC pin.
When the DV_CC is below approximately 1V, the I²C serial
port is cleared and the buck-boost switching regulator is
set to full scale.
Bus Speed
The I²C port is designed to be operated at speeds of up
to 400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I²C compliant master
device. It also contains input filters designed to suppress
glitches should the bus become corrupted.
Start and Stop Condition
A bus master signals the beginning of a communication
to a slave device by transmitting a Start condition. A Start
condition is generated by transitioning SDA from high
to low while SCL is high. When the master has finished
communicating with the slave, it issues a Stop condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for communication with another I²C
device.
Byte Format
Each byte sent to the LTC3567 must be eight bits long
followed by an extra clock cycle for the Acknowledge bit
to be returned by the LTC3567. The data should be sent
to the LTC3567 most significant bit (MSB) first.
Acknowledge
The Acknowledge signal is used for handshaking be-
tween the master and the slave. An Acknowledge (active
low) generated by the slave (LTC3567) lets the master
know that the latest byte of information was received.
The Acknowledge related clock pulse is generated by the
master. The master releases the SDA line (high) during
the Acknowledge clock cycle. The slave receiver must pull
down the SDA line during the Acknowledge clock pulse
so that it remains a stable low during the high period of
this clock pulse.
Slave Address
The LTC3567 responds to only one 7-bit address which
has been factory programmed to 0001001. The LSB of the
address byte is 1 for Read and 0 for Write. This device is
write only corresponding to an address byte of 00010010
(0x12). If the correct seven bit address is given but the
R/W bit is 1, the LTC3567 will not respond.
Bus Write Operation
The master initiates communication with the LTC3567
with a Start condition and a 7-bit address followed by
the Write Bit R/W = 0. If the address matches that of the
LTC3567, the LTC3567 returns an Acknowledge. The master
should then deliver the most significant data byte. Again
the LTC3567 acknowledges and the cycle is repeated for
3567f
17