LTC3731 Datasheet, PDF (24/32 Pages) Linear Technology – 3-Phase, 600kHz, Synchronous Buck Switching Regulator Controller

LTC3731
APPLICATIO S I FOR ATIO
1) Are the signal and power ground paths isolated? Keep the
SGND at one end of a printed circuit path thus preventing
MOSFET currents from traveling under the IC. The IC signal
ground pin should be used to hook up all control circuitry
on one side of the IC, routing the copper through SGND,
under the IC covering the “shadow” of the package, connect-
ing to the PGND pin and then continuing on to the (–) plates
of C_IN and C_OUT. The V_CC decoupling capacitor should be
placed immediately adjacent to the IC between the V_CC pin
and PGND. A 1µF ceramic capacitor of the X7R or X5R type
is small enough to fit very close to the IC to minimize the ill
effects of the large current pulses drawn to drive the bottom
MOSFETs. An additional 5µF to 10µF of ceramic, tantalum
or other very low ESR capacitance is recommended in or-
der to keep the internal IC supply quiet. The power ground
returns to the sources of the bottom N-channel MOSFETs,
anodes of the Schottky diodes and (–) plates of C_IN, which
should have as short lead lengths as possible.
2) Does the IC IN⁺ pin connect to the (+) plates of C_OUT?
A 30pF to 300pF feedforward capacitor between the IN⁺
and EAIN pins should be placed as close as possible to
the IC.
3) Are the SENSE^– and SENSE⁺ printed circuit traces for
each channel routed together with minimum PC trace
spacing? The filter capacitors between SENSE⁺ and SENSE^–
for each channel should be as close as possible to the pins
of the IC. Connect the SENSE^– and SENSE⁺ pins to the
pads of the sense resistor as illustrated in Figure 12.
4) Do the (+) plates of C_PWR connect to the drains of the
topside MOSFETs as closely as possible? This capacitor
provides the pulsed current to the MOSFETs.
5) Keep the switching nodes, SWITCH, BOOST and TG
away from sensitive small-signal nodes (SENSE⁺,
SENSE^–, IN⁺, IN^–, EAIN). Ideally the SWITCH, BOOST and
TG printed circuit traces should be routed away and
separated from the IC and especially the “quiet” side of the
IC. Separate the high dv/dt traces from sensitive small-
signal nodes with ground traces or ground planes.
6) Use a low impedance source such as a logic gate to drive
the PLLIN pin and keep the lead as short as possible.
7) The 47pF to 330pF ceramic capacitor between the I_TH
pin and signal ground should be placed as close as
possible to the IC.
Figure 11 illustrates all branch currents in a three-phase
switching regulator. It becomes very clear after studying
the current waveforms why it is critical to keep the high
switching current paths to a small physical size. High elec-
tric and magnetic fields will radiate from these “loops” just
as radio stations transmit signals. The output capacitor
ground should return to the negative terminal of the input
capacitor and not share a common ground path with any
switched current paths. The left half of the circuit gives rise
to the “noise” generated by a switching regulator. The
ground terminations of the synchronous MOSFETs and
Schottky diodes should return to the bottom plate(s) of the
input capacitor(s) with a short isolated PC trace since very
high switched currents are present. A separate isolated path
from the bottom plate(s) of the input and output capacitor(s)
should be used to tie in the IC power ground pin (PGND).
This technique keeps inherent signals generated by high
current pulses taking alternate current paths that have fi-
nite impedances during the total period of the switching
INDUCTOR
LTC3731
SENSE⁺
SENSE^–
1000pF
SENSE
RESISTOR
3731 F12b
OUTPUT CAPACITOR
Figure 12. Kelvin Sensing R_SENSE
3731fa
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