LTC3731 Datasheet, PDF (10/32 Pages) Linear Technology – 3-Phase, 600kHz, Synchronous Buck Switching Regulator Controller

LTC3731
U
OPERATIO (Refer to Functional Diagram)
Main Control Loop
The IC uses a constant frequency, current mode step-
down architecture. During normal operation, each top
MOSFET is turned on each cycle when the oscillator sets
the RS latch, and turned off when the main current
comparator, I₁, resets each RS latch. The peak inductor
current at which I₁ resets the RS latch is controlled by the
voltage on the I_TH pin, which is the output of the error
amplifier EA. The EAIN pin receives a portion of output
voltage feedback signal via the DIFFOUT pin through the
external resistive divider and is compared to the internal
reference voltage. When the load current increases, it
causes a slight decrease in the EAIN pin voltage relative to
the 0.6V reference, which in turn causes the I_TH voltage to
increase until each inductor’s average current matches
one third of the new load current (assuming all three
current sensing resistors are equal). In Burst Mode opera-
tion and Stage Shedding mode, after each top MOSFET
has turned off, the bottom MOSFET is turned on until either
the inductor current starts to reverse, as indicated by
current comparator I₂, or the beginning of the next cycle.
The top MOSFET drivers are biased from floating boot-
strap capacitor C_B, which is normally recharged through
an external Schottky diode when the top FET is turned off.
When V_IN decreases to a voltage close to V_OUT, however,
the loop may enter dropout and attempt to turn on the top
MOSFET continuously. The dropout detector counts the
number of oscillator cycles that the bottom MOSFET
remains off and periodically forces a brief on period to
allow C_B to recharge.
The main control loop is shut down by pulling the RUN/SS
pin low. Releasing RUN/SS allows an internal 1.5µA
current source to charge soft-start capacitor C_SS. When
C_SS reaches 1.5V, the main control loop is enabled and the
internally buffered I_TH voltage is clamped but allowed to
ramp as the voltage on C_SS continues to ramp. This “soft-
start” clamping prevents abrupt current from being drawn
from the input power source. When the RUN/SS pin is low,
all functions are kept in a controlled state. The RUN/SS pin
is pulled low when the supply input voltage is below 4V,
when the undervoltage lockout pin (UVADJ) is below 1.2V,
or when the IC die temperature rises above 150°C.
10
Low Current Operation
The FCB pin is a logic input to select between three modes
of operation.
A) Burst Mode Operation
When the FCB pin voltage is below 0.6V, the controller
performs as a continuous, PWM current mode synchro-
nous switching regulator. The top and bottom MOSFETs
are alternately turned on to maintain the output voltage
independent of direction of inductor current. When the
FCB pin is below V_CC – 1.5V but greater than 0.6V, the
controller performs as a Burst Mode switching regulator.
Burst Mode operation sets a minimum output current level
before turning off the top switch and turns off the synchro-
nous MOSFET(s) when the inductor current goes nega-
tive. This combination of requirements will, at low current,
force the I_TH pin below a voltage threshold that will
temporarily shut off both output MOSFETs until the output
voltage drops slightly. There is a burst comparator having
60mV of hysteresis tied to the I_TH pin. This hysteresis
results in output signals to the MOSFETs that turn them on
for several cycles, followed by a variable “sleep” interval
depending upon the load current. The resultant output
voltage ripple is held to a very small value by having the
hysteretic comparator after the error amplifier gain block.
B) Stage Shedding Operation
When the FCB pin is tied to the V_CC pin, Burst Mode
operation is disabled and the forced minimum inductor
current requirement is removed. This provides constant
frequency, discontinuous current operation over the wid-
est possible output current range. At approximately 10%
of maximum designed load current, the second and third
output stages are shut off and the phase 1 controller alone
is active in discontinuous current mode. This “stage
shedding” optimizes efficiency by eliminating the gate
charging losses and switching losses of the other two
output stages. Additional cycles will be skipped when the
output load current drops below 1% of maximum de-
signed load current in order to maintain the output volt-
age. This stage shedding operation is not as efficient as
Burst Mode operation at very light loads, but does provide
lower noise, constant frequency operating mode down to
very light load conditions.
3731fa