LTC3613 Datasheet, PDF (24/36 Pages) Linear Technology – 24V, 15A Monolithic Step Down Regulator

LTC3613
APPLICATIONS INFORMATION
To further limit current in the event of a short circuit to
ground, the LTC3613 includes foldback current limiting.
If the output fails by more than 50%, then the maximum
sense voltage is progressively lowered to about one-fourth
of its full value.
If the output exceeds 7.5% of the programmed value,
then it is considered as an overvoltage (OV) condition.
In such a case, the top MOSFET is immediately turned
off and the bottom MOSFET is turned on indefinitely until
the OV condition is removed. Current limiting is not ac-
tive during an OV. If the output returns to a nominal level,
then normal operation resumes. If the OV persists a long
time, the current through the inductor could exceed its
maximum rating.
OPTI-LOOP Compensation
OPTI-LOOP compensation, through the availability of the
ITH pin, allows the transient response to be optimized for
a wide range of loads and output capacitors. The ITH pin
not only allows optimization of the control loop behavior
but also provides a test point for the step-down regulator’s
DC-coupled and AC-filtered closed-loop response. The DC
step, rise time and settling at this test point truly reflects the
closed-loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at this pin.
The ITH series R_ITH-C_ITH1 filter sets the dominant pole-zero
loop compensation. Additionally, a small capacitor placed
from the ITH pin to SGND, C_ITH2, may be required to at-
tenuate high frequency noise. The values can be modified
to optimize transient response once the final PCB layout
is done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because their various types and values determine
the loop feedback factor gain and phase. An output current
pulse of 20% to 100% of full load current having a rise
time of 1μs to 10μs will produce output voltage and ITH
pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop. The general
goal of OPTI-LOOP compensation is to realize a fast but
stable ITH response with minimal output droop due to
the load step. For a detailed explanation of OPTI-LOOP
compensation, refer to Application Note 76.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V_OUT im-
mediately shifts by an amount equal to ΔI_LOAD • ESR, where
ESR is the effective series resistance of C_OUT. ΔI_LOAD also
begins to charge or discharge C_OUT, generating a feedback
error signal used by the regulator to return V_OUT to its
steady-state value. During this recovery time, V_OUT can
be monitored for overshoot or ringing that would indicate
a stability problem.
Connecting a resistive load in series with a power MOSFET,
then placing the two directly across the output capacitor
and driving the gate with an appropriate signal generator
is a practical way to produce a realistic load-step condi-
tion. The initial output voltage step resulting from the step
change in output current may not be within the bandwidth
of the feedback loop, so this signal cannot be used to
determine phase margin. This is why it is better to look
at the ITH pin signal which is in the feedback loop and
is the filtered and compensated feedback loop response.
The gain of the loop increases with R_ITH and the bandwidth
of the loop increases with decreasing C_ITH1. If R_ITH is
increased by the same factor that C_ITH1 is decreased, the
zero frequency will be kept the same, thereby keeping the
phase the same in the most critical frequency range of the
feedback loop. In addition, a feedforward capacitor, C_FF, can
be added to improve the high frequency response, as shown
in Figure 1. Capacitor C_FF provides phase lead by creating
a high frequency zero with R_FB2 which improves the phase
margin. The output voltage settling behavior is related to
the stability of the closed-loop system and will demonstrate
overall performance of the step-down regulator.
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