LTC3613 Datasheet, PDF (23/36 Pages) Linear Technology – 24V, 15A Monolithic Step Down Regulator

LTC3613
APPLICATIONS INFORMATION
Minimum On-Time, Minimum Off-Time
and Dropout Operation
The minimum on-time is the smallest duration of time in
which the LTC3613 can keep its top power MOSFET in its
on state. This minimum on-time is 65ns for the LTC3613
and is achieved when the V_OUT pin is tied to its minimum
value of 0.6V while the PV_IN is tied to its maximum value
of 24V. For larger values of V_OUT or smaller values of
PV_IN, the minimum on-time achievable will be longer than
65ns. The minimum on-time will have a dependency on
the operating conditions of the switching regulator, but is
intended to be smaller for high step-down ratio applica-
tions that will require low on-times.
In continuous mode operation, the minimum on-time limit
imposes a minimum duty cycle of:
D_MIN = f • t_ON(MIN)
where t_ON(MIN) is the minimum on-time for the switching
regulator. As the equation shows, reducing the operating
frequency will alleviate the minimum duty cycle constraint.
If the application requires a smaller than minimum duty
cycle, the output voltage will still remain in regulation, but
the switching frequency will decrease from its programmed
value or lose frequency synchronization if using an external
clock. Depending on the application, this may not be of
critical importance.
The minimum off-time is the smallest duration of time
that the top power MOSFET can be turned off and then
immediately turned back on. The minimum off-time that
the LTC3613 can achieve is 105ns.
The minimum off-time limit imposes a maximum duty
cycle of:
D_MAX = 1 – f • t_OFF(MIN)
where t_OFF(MIN) is the minimum off-time of the switching
regulator. Reducing the operating frequency alleviates the
maximum duty cycle constraint. If the maximum duty cycle
is reached, due to a drooping input voltage for example,
then the output will drop out of regulation. The minimum
input voltage to avoid dropout is:
V_IN(M
IN)
=
V_OUT
D_MAX
At the onset of dropout, there is a region of PV_IN about
500mV that generates two discrete off-times, one being
the minimum off-time and the other being an off-time that
is about 40ns to 60ns larger than the minimum off-time.
This secondary off-time is due to the longer delay in trip-
ping the internal current comparator. The two off-times
average out to the required duty cycle to keep the output
in regulation with the output ripple remaining the same.
However, there is higher SW node jitter, especially appar-
ent when synchronized to an external clock. Depending
on the application, this may not be of critical importance.
Fault Conditions: Current Limiting and Overvoltage
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage.
In the LTC3613, the maximum sense voltage is controlled
by the voltage on the V_RNG pin. With valley current mode
control, the maximum sense voltage and the sense re-
sistance determine the maximum allowed inductor valley
current. The corresponding output current limit is:
I_LIMIT
=
V_SENSE(MAX)
R_SENSE
+
1
2
•
ΔI_L
The current limit value should be checked to ensure that
I_LIMIT(MIN) > I_OUT(MAX). The current limit value should
be greater than the inductor current required to produce
maximum output power at the worst-case efficiency.
Worst-case efficiency typically occurs at the highest PV_IN
and highest ambient temperature.
3613fa
23