LTC3613 Datasheet, PDF (22/36 Pages) Linear Technology – 24V, 15A Monolithic Step Down Regulator

LTC3613
APPLICATIONS INFORMATION
calculated on-time (see Efficiency Considerations). For
these circumstances, the voltage on the V_OUT pin can
be programmed with a resistive divider from INTV_CC or
from the regulator’s output itself. Note that there is a 500k
nominal resistance looking into the V_OUT pin.
The PLL adjusted on-time achieved after phase locking is
the steady-state on-time required by the switching regula-
tor, and if the V_OUT programmed on-time is substantially
equal to this steady-state on-time, then the PLL system
does not have to use its ±30% frequency lock range for
systematic corrections. Instead the lock range can be used
to correct for component variations or other operating point
conditions. If needed, the V_OUT pin can be programmed to
achieve the steady-state on-time as required by the applica-
tion and therefore maintain constant frequency operation.
If the application requires very low on-times approaching
minimum on-time, the PLL system may not be able to
maintain a ±30% synchronization range. In fact, there is
a possibility of losing phase/frequency lock at minimum
on-time, and definitely losing phase/frequency lock for
applications requiring less than minimum on-time. This
is discussed further under Minimum On-Time, Minimum
Off-Time and Dropout Operation.
During dynamic transient conditions either in the line or
load (e.g., load step or release), the LTC3613 may lose
phase and frequency lock in the process of achieving
faster transient response. For large slew rates (e.g., 10A/
μs), phase and frequency lock will be lost (see Figure 8)
until the system returns back to a steady-state condition
at which point the device will resume frequency lock and
eventually achieve phase lock to the external clock. For
relatively small slew rates (10A/s), phase and frequency
lock can still be maintained.
For light loading conditions, the phase and frequency
synchronization will be active if there is a clock input ap-
plied. If there is no clock input during light loading, then
the switching frequency is based on what the MODE/PLLIN
pin is tied to. When MODE/PLLIN is tied to INTV_CC, the
LTC3613 will operate in forced continuous mode at the RT
programmed free-running frequency. When MODE/PLLIN
pin is tied to signal ground, the LTC3613 will operate in
pulse-skipping discontinuous conduction mode for light
loading and will switch to continuous conduction (at the
free-running frequency) for normal and heavy loads.
I_LOAD
CLOCK
INPUT
PHASE LOCKED
SW
LOSES PHASE
LOCK DUE
TO FAST
LOAD STEP
ESTABLISHES
FREQUENCY
LOCK SOON
ESTABLISHES
PHASE LOCK
AFTER ~600μs
LOSES PHASE
LOCK DUE TO
FAST LOAD
RELEASE
ESTABLISHES
FREQUENCY
LOCK SOON
V_OUT
3613 F08
Figure 8. Phase and Frequency Locking Behavior During Transient Load Conditions
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