LTC3566-2_15 Datasheet, PDF (24/28 Pages) Linear Technology – High Efficiency USB Power Manager Plus 1A Buck-Boost Converter

LTC3566/LTC3566-2
APPLICATIONS INFORMATION
smaller 0805 case. The size of the input overshoot will be
determined by the Q of the resonant tank circuit formed
by C_IN and the input lead inductance. It is recommended
to measure the input ringing with the selected compo-
nents to verify compliance with the Absolute Maximum
specifications.
Alternatively, the following soft connect circuit (Figure 5)
can be employed. In this circuit, capacitor C1 holds MP1
off when the cable is first connected. Eventually C1 begins
to charge up to the USB input voltage applying increasing
gate support to MP1. The long time constant of R1 and
C1 prevent the current from building up in the cable too
fast thus dampening out any resonant overshoot.
Buck-Boost Regulator Output Voltage Programming
The buck-boost regulator can be programmed for output
voltages greater than 2.75V and less than 5.5V. The output
voltage is programmed using a resistor divider from the
V_OUT1 pin connected to the FB1 pin such that:
V_OUT1
=
V_FB1
^ _RRF¹_B
+

1

where V_FB1 is fixed at 0.8V (see Figure 6).
Closing the Feedback Loop
The LTC3566 family incorporates voltage mode PWM
control. The control to output gain varies with operation
region (buck, boost, buck-boost), but is usually no greater
than 20. The output filter exhibits a double pole response
given by:
f _{FILTER _POLE} = _{2 • π •}
1
Hz
L • C_OUT
5V USB
INPUT _{USB CABLE}
MP1
Si2333
C1
100nF
R1
40k
V_BUS
C2
10μF
LTC3566/
LTC3566-2
GND
3566 F05
Figure 5. USB Soft Connect Circuit
24
Where C_OUT is the output filter capacitor.
The output filter zero is given by:
f
FILTER
_
ZERO
=
2
•
π
1
• R_ESR
•
C_OUT
Hz
where R_ESR is the capacitor equivalent series resis-
tance.
A troublesome feature in boost mode is the right-half plane
zero (RHP), and is given by:
f
RHPZ ⁼
2
•
π
V_IN12
•I_OUT •L
•
Hz
V_OUT1
The loop gain is typically rolled off before the RHP zero
frequency.
A simple Type I compensation network (as shown in
Figure 6), can be incorporated to stabilize the loop but
at the cost of reduced bandwidth and slower transient
response. To ensure proper phase margin, the loop must
cross unity-gain a decade before the LC double pole.
The unity-gain frequency of the error amplifier with the
Type I compensation is given by:
f
UG
=
2
•
π
•
1
R1•
C_P1
Hz
Most applications demand an improved transient response
to allow a smaller output filter capacitor. To achieve a higher
bandwidth, Type III compensation is required. Two zeros
are required to compensate for the double-pole response.
Type III compensation also reduces any V_OUT1 overshoot
seen at start-up.
The compensation network depicted in Figure 7 yields the
transfer function:
V_C1
V_OUT1
=
R1•
1
(^C1+
C2₎
•
(^{1+ sR2C2}) ^• (^{1+ s(R1+R3)C3})
s
•

₁₊
sR2C1C2
C1+ C2


•
(¹⁺
sR3C3₎
3566fb