LTC3807_15 Datasheet, PDF(23/32 Page) Linear Technology – Low IQ, Synchronous Step-Down Controller with 24V Output Voltage Capability

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LTC3807_15 Datasheet, PDF (23/32 Pages) Linear Technology – Low IQ, Synchronous Step-Down Controller with 24V Output Voltage Capability

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LTC3807

APPLICATIONS INFORMATION

Phase-Locked Loop and Frequency Synchronization

The LTC3807 has an internal phase-locked loop (PLL)

comprised of a phase frequency detector, a lowpass filter,

and a voltage-controlled oscillator (VCO). This allows the

turn-on of the top MOSFET to be locked to the rising edge

of an external clock signal applied to the PLLIN/MODE pin.

The phase detector is an edge sensitive digital type that

provides zero degrees phase shift between the external

and internal oscillators. This type of phase detector does

not exhibit false lock to harmonics of the external clock.

If the external clock frequency is greater than the inter-

nal oscillatorâs frequency, fOSC, then current is sourced

continuously from the phase detector output, pulling up

the VCO input. When the external clock frequency is less

than fOSC, current is sunk continuously, pulling down the

VCO input.

If the external and internal frequencies are the same but

exhibit a phase difference, the current sources turn on for

an amount of time corresponding to the phase difference.

The voltage at the VCO input is adjusted until the phase

and frequency of the internal and external oscillators are

identical. At the stable operating point, the phase detector

output is high impedance and the internal filter capacitor,

CLP, holds the voltage at the VCO input.

Note that the LTC3807 can only be synchronized to an

external clock whose frequency is within range of the

LTC3807âs internal VCO, which is nominally 55kHz to

900kHz.

This is guaranteed to be between 75kHz and 750kHz. Typi-

cally, the external clock (on the PLLIN/MODE pin) input high

threshold is 1.6V, while the input low threshold is 1.1V.

Rapid phase locking can be achieved by using the FREQ pin

to set a free-running frequency near the desired synchro-

nization frequency. The VCOâs input voltage is prebiased

at a frequency corresponding to the frequency set by the

FREQ pin. Once prebiased, the PLL only needs to adjust

the frequency slightly to achieve phase lock and synchro-

nization. Although it is not required that the free-running

frequency be near external clock frequency, doing so will

prevent the operating frequency from passing through a

large range of frequencies as the PLL locks.

1000

900

800

700

600

500

400

300

200

100

15 25 35 45 55 65 75 85 95 105 115 125

3807 F09

Figure 9. Relationship Between Oscillator Frequency and

Resistor Value at the FREQ Pin

Table 2 summarizes the different states in which the FREQ

pin can be used.

Table 2

FREQ PIN

INTVCC

Resistor

Any of the Above

PLLIN/MODE PIN

DC Voltage

External Clock

FREQUENCY

350kHz

535kHz

50kHz to 900kHz

Phase Locked to

External Clock

Minimum On-Time Considerations

Minimum on-time, tON(MIN), is the smallest time duration

that the LTC3807 is capable of turning on the top MOSFET.

It is determined by internal timing delays and the gate

For more information www.linear.com/LTC3807

3807f

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