LTC3807_15 Datasheet, PDF (14/32 Pages) Linear Technology – Low IQ, Synchronous Step-Down Controller with 24V Output Voltage Capability

LTC3807
OPERATION
LTC3807’s phase detector adjusts the voltage (through an
internal lowpass filter) of the VCO input to align the turn-on
of the controller’s external top MOSFET to the rising edge
of the synchronizing signal.
The VCO input voltage is prebiased to the operating fre-
quency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
The typical capture range of the phase-locked loop is from
approximately 55kHz to 900kHz, with a guarantee to be
between 75kHz and 750kHz. In other words, the LTC3807’s
PLL is guaranteed to lock to an external clock source whose
frequency is between 75kHz and 750kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling). It is recommended
that the external clock source swing from ground (0V) to
at least 2.5V.
Output Overvoltage Protection
An overvoltage comparator guards against transient over-
shoots as well as other more serious conditions that may
overvoltage the output. When the V_FB pin rises by more
than 10% above its regulation point of 0.800V, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Power Good Pin
The PGOOD pin is connected to an open drain of an internal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD pin low when the V_FB pin voltage is not within ±10%
of the 0.8V reference voltage. The PGOOD pin is also pulled
low when the RUN pin is low (shut down). When the V_FB
pin voltage is within the ±10% requirement, the MOSFET
is turned off and the pin is allowed to be pulled up by an
external resistor to a source no greater than 6V.
Foldback Current
When the output voltage falls to less than 70% of its
nominal level, foldback current limiting is activated, pro-
gressively lowering the peak current limit in proportion to
the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
interval (as long as the V_FB voltage is keeping up with the
TRACK/SS voltage).
3807f
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For more information www.linear.com/LTC3807