LTC3733_15 Datasheet, PDF (23/32 Pages) Linear Technology – 3-Phase, Buck Controllers for AMD CPUs

LTC3733/LTC3733-1
APPLICATIO S I FOR ATIO
The I_TH series R_C-C_C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to maximize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon because the various types and values determine the
loop feedback factor gain and phase. An output current
pulse of 20% to 80% of full load current having a rise time
of <2µs will produce output voltage and I_TH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop. The initial output voltage step,
resulting from the step change in output current, may not
be within the bandwidth of the feedback loop, so this signal
cannot be used to determine phase margin. This is why it
is better to look at the I_TH pin signal which is in the
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased by
increasing R_C and the bandwidth of the loop will be
increased by decreasing C_C. If R_C is increased by the same
factor that C_C is decreased, the zero frequency will be kept
the same, thereby keeping the phase the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual over-
all supply performance.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C_OUT, causing a rapid drop in V_OUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If C_LOAD is greater
than 2% of C_OUT , the switch rise time should be controlled
so that the load rise time is limited to approximately
1000 • R_SENSE • C_LOAD. Thus a 250µF capacitor and a 2mΩ
R_SENSE resistor would require a 500µs rise time, limiting
the charging current to about 1A.
Design Example (Using Three Phases)
As a design example, assume V_IN = 12V(nominal), V_IN =
20V(max), V_OUT = 1.3V, I_MAX = 45A and f = 400kHz. The
inductance value is chosen first based upon a 30% ripple
current assumption. The highest value of ripple current in
each output stage occurs at the maximum input voltage.
L
=
V_OUT
f₍∆I₎
_1−
V_OUT
V_IN


=
1.3V
(^400kHz)(^30%)(^15A)
_1−
1.3V
20V

≥ 0.68µH
Using L = 0.6µH, a commonly available value results in
34% ripple current. The worst-case output ripple for the
three stages operating in parallel will be less than 11% of
the peak output current.
R_SENSE1, R_SENSE2 and R_SENSE3 can be calculated by using
a conservative maximum sense current threshold of 65mV
and taking into account half of the ripple current:
R_SENSE
=
65mV
15A^{}1+ ^{342%}
=
0.0037Ω
Use a commonly available 0.003Ω sense resistor.
Next verify the minimum on-time is not violated. The
minimum on-time occurs at maximum V_CC:
t_ON(MIN)
=
V_OUT
( ) ^V_IN(MAX) ^f
=
1.3V
20V₍400kHz₎
=
162ns
3733f
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