LTC3546_15 Datasheet, PDF (23/30 Pages) Linear Technology – Dual Synchronous, 3A/1A or 2A/2A Configurable Step-Down DC/DC Regulator

LTC3546
Applications Information
operating frequency of 1.5MHz and assumes roughly a
300mA/A load step.
C_OUT1
=
22µF
A
• 0.8A
•
280mA
300mA _{• 0.8A}
=
20.5µF
A
C_OUT1
=
22µF
A
• 2.5A
•
875mA
300mA _{• 2.5A}
=
64.2µF
A
The closest values are 22µF and 68µF.
The output voltages can now be programmed by choos-
ing the values of R1, R2, R3, and R4. To maintain high
efficiency, the current in these resistors should be kept
small. Choosing 2µA with the 0.6V feedback voltages
makes R2 and R4 equal to 300k. A close standard 1%
resistor is 301k. This then makes R1 = 300k. A close
standard 1% is 301k. R3 then equals 600k. A close 1%
resistor is 604k.
The compensation should be optimized for these com-
ponents by examining the load step response but a good
place to start for the LTC3546 is with a 13kΩ and 1000pF
filter on both I_TH1 and I_TH2. The output capacitor may
need to be increased depending on the actual transient
during a load step.
The PGOOD pin is a common drain output and requires a
pull-up resistor. A 100k resistor is used for adequate speed.
Figure 9 shows a complete schematic for this design.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3546. These items are also illustrated graphically
in the layout diagram of Figure 7. Check the following in
your layout.
1. Make sure SW1, SW2A, SW2B and SW1D are connected
on the PC board through a wide piece of copper.
2. All, or part, of C_IN should connect from Pin 9 to Pin 14
on the same side of the PC board as the chip and as
close to the chip as possible, where the SW traces will go
directly under the capacitor. C_IN provides the AC current
to the internal power MOSFETs and their drivers.
3. Are the respective C_OUT, L closely connected? The (–)
plate of C_OUT1 returns current to PGND1, and the (–)
plate of C_OUT2 returns current to the PGND2. The (–)
plate of C_IN should also return current to PGND1 and
PGND2.
4. The resistor divider, R1 and R2, must be connected
between the (+) plate of C_OUT1 and a ground line ter-
minated near GNDA. The resistor divider R3 and R4,
must be connected between the (+) plate of C_OUT2 and
the ground connection terminated to the GNDA pin.
The feedback signals V_FB1 and V_FB2 should be routed
away from noise components and traces, such as the
SW lines, and its trace should be minimized.
5. When using the R_FREQ resistor, the ground connection
of the resistor should be terminated to the GNDA pin.
When using the internal PLL, the ground connection of
the R-C compensation network should be terminated
to the GNDA pin.
6. Keep sensitive components away from the SW pins.
The input capacitor C_IN, the compensation capacitors
C_FF1, C_FF2, C_ITH1, and C_ITH2 and all resistors R1, R2,
R3, R4, R_ITH1 and R_ITH2 should be routed away from
the SW traces and the inductors L1 and L2.
7. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the SGND pin at one
point which is then connected to the PGND1/PGND2/
PGND1D/GNDD pins.
8. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to the Exposed Pad (Pin 29).
For more information www.linear.com/3546
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