LTC3546_15 Datasheet, PDF (20/30 Pages) Linear Technology – Dual Synchronous, 3A/1A or 2A/2A Configurable Step-Down DC/DC Regulator

LTC3546
Applications Information
ulators. This mode provides the best low current efficiency
at the cost of a higher output voltage ripple. When SYNC/
MODE is connected to ground, pulse-skipping operation is
selected for both regulators. This mode provides a lower
output voltage and current ripple at the cost of low current
efficiency. Applying V_IN/2 results in forced continuous mode
for both regulators. This mode creates a fixed output ripple
and is capable of sinking some current (about 1/2 • ΔI_L).
Since the switching noise is constant in this mode, it is also
the easiest to filter out. During initial start-up, pulse-skipping
mode is forced until the PGOOD pin goes high.
The LTC3546 can also be synchronized to an external
clock signal by the SYNC/MODE pin. An internal phase
locked loop locks to the incoming signal to provide for
180° out-of-phase operation as well as correct slope
compensation. With external synchronization the FREQ
pin is used for externally compensating the internal phase
locked loop. Typical values used for compensation are 200k
and 100pf, as shown in Figure 6. During synchronization,
the regulator operating mode is forced to pulse skipping.
The P-channel switch turn on is synchronized to the rising
edge of the external clock.
When using an external clock, with the PHASE pin low, the
switching of the two channels occur 180° out-of-phase.
estimated using the percentage of overshoot seen at this
pin, or by examining the rise time at this pin.
The I_TH external components shown in the Figure 9 circuit
will provide an adequate starting point for most applica-
tions. The series R-C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because of various types and values determine the loop
feedback factor gain and phase. An output current pulse
of 20% to 100% of full load current having a rise time
of 1µs to 10µs will produce output voltage and I_TH pin
waveforms that will give a sense of overall loop stability
without breaking the feedback loop.
Switching regulators take several cycles to respond to
a step in load current. When a load step occurs, V_OUT
immediately shifts by an amount equal to ΔI_LOAD • ESR,
where ESR is the effective series resistance of C_OUT. The
ΔI_LOAD also begins to charge or discharge C_OUT generating
a feedback error signal used by the regulator to return
V_OUT to its steady-state value. During this recovery time,
V_OUT can be monitored for overshoot or ringing that would
indicate a stability problem.
LTC3546
FREQ
3546 F06
200k
100pF
Figure 6. PLL Compensation
Checking Transient Response
The I_TH pin compensation allows the transient response
to be optimized for a wide range of loads and output
capacitors. The availability of the I_TH pin not only allows
optimization of the control loop behavior but also pro-
vides a DC-coupled and AC filtered closed loop response
test point. The DC step, rise time and settling at this test
point truly reflects the closed loop response. Assuming a
predominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
The initial output voltage step may not be within the band-
width of the feedback loop, so the standard second order
overshoot/DC ratio cannot be used to determine phase
margin. The gain of the loop increases with R_ITH and the
bandwidth of the loop increases with decreasing C_ITH. If
R_ITH is increased by the same factor that C_ITH is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. In addition, feedforward capacitors,
C_FF1 and C_FF2, can be added to improve the high frequency
response, as shown in Figure 9. Capacitor C_FF1 provides
phase lead by creating a high frequency zero with R1
which improves the phase margin for the 1A SW1 chan-
nel. Capacitor C_FF2 provides phase lead by creating a high
frequency zero with R3 which improves the phase margin
for the 3A SW1D/SW2 channel.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
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