LTC6992-1 Datasheet, PDF (21/32 Pages) Linear Technology – TimerBlox Voltage-Controlled Pulse Width Modulator (PWM)

LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
APPLICATIONS INFORMATION
At the other extreme, it is not recommended to operate
the master oscillator beyond 2MHz because the accuracy
of the DIV pin ADC will suffer.
Pulse Width Modulation Bandwidth and Settling Time
The LTC6992 will respond to changes in V_MOD up to a –3dB
bandwidth of TBD (see Figure 10). This makes it easy to
stabilize a feedback loop around the LTC6992, since it
does not introduce a low frequency pole.
Duty cycle settling time depends on the master oscillator
frequency. Following a ±100mV step change in V_MOD, the
duty cycle takes approximately TBD master clock cycles
(TBD • t_MASTER) to settle to within 1% of the final value.
An example is shown in Figure 11.
Frequency Modulation and Settling Time
In addition to pulse-width modulation, the LTC6992 can
be frequency modulated by varying I_SET. The LTC6992
will respond to changes in I_SET up to a –3dB bandwidth
of TBD • f_OUT (see Figure 12).
Following a 2x or 0.5x step change in I_SET, the output
frequency takes approximately TBD master clock cycles
(TBD • t_MASTER) to settle to within 1% of the final value.
An example is shown in Figure 13.
PLACEHOLDER
Figure 10. PWM Frequency Response
PLACEHOLDER
Figure 11. PWM Settling Time
PLACEHOLDER
Figure 12. Frequency Modulation Bandwidth
PLACEHOLDER
Figure 13. Frequency Change Settling Time
69921234p
21