LTC6992-1 Datasheet, PDF (18/32 Pages) Linear Technology – TimerBlox Voltage-Controlled Pulse Width Modulator (PWM)

LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
OPERATION
Changing DIVCODE After Start-Up
Following start-up, the A/D converter will continue
monitoring V_DIV for changes. Changes to DIVCODE will
be recognized slowly, as the LTC6992 places a priority on
eliminating any “wandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
t_DIVCODE = 16 • (ΔDIVCODE + 6) • t_MASTER
A change in DIVCODE will not be recognized until it is
stable, and will not pass through intermediate codes.
A digital filter is used to guarantee the DIVCODE has settled
to a new value before making changes to the output. Then
the output will make a clean (glitchless) transition to the
new divider setting.
Start-Up Time
When power is first applied to the LTC6992 the power-on
reset (POR) circuit will initiate the start-up time, t_START.
The OUT pin is held low during this time. The typical value
for t_START ranges from 0.5ms to 8ms depending on the
master oscillator frequency (independent of N_DIV):
t_START(TYP) = 500 • t_MASTER
The output will begin oscillating after t_START. If POL = 0
the first pulse has the correct width. If POL = 1 (DIVCODE
≥ 8), the first pulse width can be shorter or longer than
expected, depending on the duty cycle setting, and will
never be less than 25% of t_OUT.
During start-up, the DIV pin A/D converter must determine
the correct DIVCODE before the output is enabled. The
start-up time may increase if the supply or DIV pin volt-
ages are not stable. For this reason, it is recommended to
minimize the capacitance on the DIV pin so it will properly
track V⁺. Less than 100pF will not affect performance.
V⁺
Figure 5. DIVCODE Change from 5 to 2
DIV
STABLE V_DIV
t_DIVCODE
t_START
OUT
1ST PULSE WIDTH MAY BE INACCURATE
6992 F06
Figure 6. Start-Up Timing Diagram
18
69921234p