LTC3808 Datasheet, PDF (21/28 Pages) Linear Technology – No RSENSE TM, Low EMI, Synchronous DC/DC Controller with Output Tracking

LTC3808
APPLICATIO S I FOR ATIO
105
V_REF
100
95
MAXIMUM
SENSE VOLTAGE
90
85
80
75
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
INPUT VOLTAGE (V)
3808 F10
Figure 10. Line Regulation of V_REF and Maximum Sense Voltage
Low Input Supply Voltage
Although the LTC3808 can function down to below 2.4V,
the maximum allowable output current is reduced as V_IN
decreases below 3V. Figure 10 shows the amount of
change as the supply is reduced down to 2.4V. Also shown
is the effect on V_REF.
Minimum On-Time Considerations
Minimum on-time, t_ON(MIN) is the smallest amount of time
that the LTC3808 is capable of turning the top P-channel
MOSFET on. It is determined by internal timing delays and
the gate charge required to turn on the top MOSFET. Low
duty cycle and high frequency applications may approach
the minimum on-time limit and care should be taken to
ensure that:
t_ON(MIN)
<
V_OUT
f_OSC • V_IN
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3808 will begin to skip
cycles (unless forced continuous mode is selected). The
output voltage will continue to be regulated, but the ripple
current and ripple voltage will increase. The minimum on-
time for the LTC3808 is typically about 210ns. However,
as the peak sense voltage (I_L(PEAK) • R_DS(ON)) decreases,
the minimum on-time gradually increases up to about
260ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If forced
continuous mode is selected and the duty cycle falls below
the minimum on time requirement, the output will be
regulated by overvoltage protection.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + …)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3808 circuits: 1) LTC3808 DC bias current,
2) MOSFET gate charge current, 3) I²R losses and
4) transition losses.
1) The V_IN (pin) current is the DC supply current, given in
the Electrical Characteristics, which excludes MOSFET
driver currents. V_IN current results in a small loss that
increases with V_IN.
2) MOSFET gate charge current results from switching the
gate capacitance of the power MOSFET. Each time a
MOSFET gate is switched from low to high to low again, a
packet of charge dQ moves from SENSE⁺ to ground. The
resulting dQ/dt is a current out of SENSE⁺, which is
typically much larger than the DC supply current. In
continuous mode, I_GATECHG = f • Q_P.
3) I²R losses are calculated from the DC resistances of the
MOSFETs, inductor and/or sense resistor. In continuous
mode, the average output current flows through L but is
“chopped” between the top P-channel MOSFET and the
bottom N-channel MOSFET. The MOSFET R_DS(ON) and/or
the resistance of the sense resistor multiplied by duty cycle
can be summed with the resistance of L to obtain I²R
losses.
4) Transition losses apply to the external MOSFET and
increase with higher operating frequencies and input volt-
ages. Transition losses can be estimated from:
Transition Loss = 2 • V_IN2 • I_O(MAX) • C_RSS • f
Other losses, including C_IN and C_OUT ESR dissipative
losses and inductor core losses, generally account for less
than 2% total additional loss.
3808f
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