LTC3808 Datasheet, PDF (10/28 Pages) Linear Technology – No RSENSE TM, Low EMI, Synchronous DC/DC Controller with Output Tracking

LTC3808
U
OPERATIO (Refer to Functional Diagram)
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3808 draws.
The load current is supplied by the output capacitor. As the
output voltage decreases, the EAMP increases the I_TH
voltage. When the I_TH voltage reaches 0.925V, the SLEEP
signal goes low and the controller resumes normal opera-
tion by turning on the external P-channel MOSFET on the
next cycle of the internal oscillator.
When the controller is enabled for Burst Mode or pulse
skipping operation, the inductor current is not allowed to
reverse. Hence, the controller operates discontinuously.
The reverse current comparator RICMP senses the drain-
to-source voltage of the bottom external N-channel
MOSFET. This MOSFET is turned off just before the
inductor current reaches zero, preventing it from going
negative.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by the
voltage on the I_TH pin. The P-channel MOSFET is turned on
every cycle (constant frequency) regardless of the I_TH pin
voltage. In this mode, the efficiency at light loads is lower
than in Burst Mode operation. However, continuous mode
has the advantages of lower output ripple and no noise at
audio frequencies.
When the SYNC/MODE pin is clocked by an external clock
source to use the phase-locked loop (see Frequency
Selection and Phase-Locked Loop), or is set to a DC
voltage between 0.4V and several hundred mV below V_IN,
the LTC3808 operates in PWM pulse skipping mode at
light loads. In this mode, the current comparator ICMP
may remain tripped for several cycles and force the
external P-channel MOSFET to stay off for the same
number of cycles. The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuous operation, exhibits low output ripple as well as
low audio noise and reduced RF interference as compared
to Burst Mode operation. However, it provides low current
efficiency higher than forced continuous mode, but not
nearly as high as Burst Mode operation. During start-up or
an undervoltage condition (V_FB ≤ 0.54V), the LTC3808
operates in pulse skipping mode (no current reversal
allowed), regardless of the state of the SYNC/MODE pin.
10
Short-Circuit and Current Limit Protection
The LTC3808 monitors the voltage drop ∆V_SC (between
the GND and SW pins) across the external N-channel
MOSFET with the short-circuit current limit comparator.
The allowed voltage is determined by:
∆V_SC(MAX) = A • 90mV
where A is a constant determined by the state of the IPRG
pin. Floating the IPRG pin selects A = 1; tying IPRG to V_IN
selects A = 5/3; tying IPRG to GND selects A = 2/3.
The inductor current limit for short-circuit protection is
determined by ∆V_SC(MAX) and the on-resistance of the
external N-channel MOSFET:
I_SC
=
∆V_SC(MAX)
R_DS(ON)
Once the inductor current exceeds I_SC, the short current
comparator will shut off the external P-channel MOSFET
until the inductor current drops below I_SC.
Output Overvoltage Protection
As further protection, the overvoltage comparator (OVP)
guards against transient overshoots, as well as other more
serious conditions that may overvoltage the output. When
the feedback voltage on the V_FB pin has risen 13.33%
above the reference voltage of 0.6V, the external P-chan-
nel MOSFET is turned off and the N-channel MOSFET is
turned on until the overvoltage is cleared.
Frequency Selection and Phase-Locked Loop
(PLLLPF and SYNC/MODE Pins)
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching losses,
but requires larger inductance and/or capacitance to main-
tain low output ripple voltage.
The switching frequency of the LTC3808’s controllers can
be selected using the PLLLPF pin. If the SYNC/MODE is
not being driven by an external clock source, the PLLLPF
can be floated, tied to V_IN or tied to GND to select 550kHz,
750kHz or 300kHz, respectively.
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