LTC3788_15 Datasheet, PDF(21/32 Page) Linear Technology – 2-Phase, Dual Output Synchronous Boost Controller

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

LTC3788_15 Datasheet, PDF (21/32 Pages) Linear Technology – 2-Phase, Dual Output Synchronous Boost Controller

◁

LTC3788

Applications Information

Each of the topside MOSFET drivers includes an internal

charge pump that delivers current to the bootstrap capaci-

tor from the BOOST pin. This charge current maintains

the bias voltage required to keep the top MOSFET on

continuously during dropout/overvoltage conditions. The

Schottky/silicon diodes selected for the topside drivers

should have a reverse leakage less than the available output

current the charge pump can supply. Curves displaying

the available charge pump current under different operat-

ing conditions can be found in the Typical Performance

Characteristics section.

A leaky diode DB in the boost converter can not only

prevent the top MOSFET from fully turning on but it can

also completely discharge the bootstrap capacitor CB and

create a current path from the input voltage to the BOOST

pin to INTVCC. This can cause INTVCC to rise if the diode

leakage exceeds the current consumption on INTVCC.

This is particularly a concern in Burst Mode operation

where the load on INTVCC can be very small. The external

Schottky or silicon diode should be carefully chosen such

that INTVCC never gets charged up much higher than its

normal regulation voltage.

Fault Conditions: Overtemperature Protection

At higher temperatures, or in cases where the internal

power dissipation causes excessive self heating on-chip

(such as an INTVCC short to ground), the overtemperature

shutdown circuitry will shut down the LTC3788. When the

junction temperature exceeds approximately 170Â°C, the

overtemperature circuitry disables the INTVCC LDO, causing

the INTVCC supply to collapse and effectively shut down

the entire LTC3788 chip. Once the junction temperature

drops back to approximately 155Â°C, the INTVCC LDO turns

back on. Long term overstress (TJ > 125Â°C) should be

avoided as it can degrade the performance or shorten

the life of the part.

Phase-Locked Loop and Frequency Synchronization

The LTC3788 has an internal phase-locked loop (PLL)

comprised of a phase frequency detector, a low pass filter

and a voltage-controlled oscillator (VCO). This allows the

turn-on of the top MOSFET of controller 1 to be locked to

the rising edge of an external clock signal applied to the

PLLIN/MODE pin. The turn-on of controller 2âs top MOSFET

is thus 180 degrees out-of-phase with the external clock.

The phase detector is an edge-sensitive digital type that

provides zero degrees phase shift between the external

and internal oscillators. This type of phase detector does

not exhibit false lock to harmonics of the external clock.

If the external clock frequency is greater than the inter-

nal oscillatorâs frequency, fOSC, then current is sourced

continuously from the phase detector output, pulling up

the VCO input. When the external clock frequency is less

than fOSC, current is sunk continuously, pulling down the

VCO input. If the external and internal frequencies are the

same but exhibit a phase difference, the current sources

turn on for an amount of time corresponding to the phase

difference. The voltage at the VCO input is adjusted until

the phase and frequency of the internal and external os-

cillators are identical. At the stable operating point, the

phase detector output is high impedance and the internal

filter capacitor, CLP, holds the voltage at the VCO input.

Typically, the external clock (on PLLIN/MODE pin) input

high threshold is 1.6V, while the input low threshold is 1.2V.

Note that the LTC3788 can only be synchronized to an

external clock whose frequency is within range of the

LTC3788âs internal VCO, which is nominally 55kHz to

1MHz. This is guaranteed to be between 75kHz and 850kHz.

Rapid phase locking can be achieved by using the FREQ pin

to set a free-running frequency near the desired synchro-

nization frequency. The VCOâs input voltage is prebiased

at a frequency corresponding to the frequency set by the

FREQ pin. Once prebiased, the PLL only needs to adjust

the frequency slightly to achieve phase lock and synchro-

nization. Although it is not required that the free-running

frequency be near external clock frequency, doing so will

prevent the operating frequency from passing through a

large range of frequencies as the PLL locks.

3788fc

▷