LTC3736_15 Datasheet, PDF(21/28 Page) Linear Technology – Dual 2-Phase, No RSENSE, Synchronous Controller with Output Tracking

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LTC3736_15 Datasheet, PDF (21/28 Pages) Linear Technology – Dual 2-Phase, No RSENSE, Synchronous Controller with Output Tracking

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LTC3736

APPLICATIO S I FOR ATIO

VIN

LTC3736

1:N

SYNC/FCB

+ VAUX

1ÂµF

VOUT

COUT

3736 F10

Figure 10. Auxiliary Output Loop Connection

If VAUX drops below this value, the FCB voltage forces

temporary continuous switching operation until VAUX is

again above its minimum.

Table 3 summarizes the different states in which the

SYNC/FCB pin can be used

Table 3

SYNC/FCB PIN

0V to 0.5V

0.7V to VIN

Feedback Resistors

External Clock Signal

CONDITION

Forced Continuous Mode

Current Reversal Allowed

Burst Mode Operation Enabled

No Current Reversal Allowed

Regulate an Auxiliary Winding

Enable Phase-Locked Loop

(Synchronize to External CLK)

Pulse-Skipping at Light Loads

No Current Reversal Allowed

Fault Condition: Short Circuit and Current Limit

To prevent excessive heating of the bottom MOSFET,

foldback current limiting can be added to reduce the

current in proportion to the severity of the fault.

Foldback current limiting is implemented by adding di-

odes DFB1 and DFB2 between the output and the ITH pin as

shown in Figure 11. In a hard short (VOUT = 0V), the current

will be reduced to approximately 50% of the maximum

output current.

Low Supply Operation

Although the LTC3736 can function down to below 2.4V,

the maximum allowable output current is reduced as VIN

decreases below 3V. Figure 12 shows the amount of

change as the supply is reduced down to 2.4V. Also shown

is the effect on VREF.

1/2 LTC3736

ITH

VFB

R2 +

VOUT

DFB1

DFB2

3736 F11

Figure 11. Foldback Current Limiting

105

VREF

100

MAXIMUM

SENSE VOLTAGE

2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0

INPUT VOLTAGE (V)

3736 F12

Figure 12. Line Regulation of VREF and

Maximum Sense Voltage for Low Input Supply

Minimum On-Time Considerations

Minimum on-time, tON(MIN), is the smallest amount of time

in which the LTC3736 is capable of turning the top

P-channel MOSFET on and then off. It is determined by

internal timing delays and the gate charge required to turn

on the top MOSFET. Low duty cycle and high frequency

applications may approach the minimum on-time limit

and care should be taken to ensure that:

tON(MIN)

VOUT

fOSC â¢ VIN

If the duty cycle falls below what can be accommodated

by the minimum on-time, the LTC3736 will begin to skip

cycles (unless forced continuous mode is selected). The

output voltage will continue to be regulated, but the ripple

current and ripple voltage will increase. The minimum on-

time for the LTC3736 is typically about 250ns. However,

as the peak sense voltage (IL(PEAK) â¢ RDS(ON)) decreases,

the minimum on-time gradually increases up to about

300ns. This is of particular concern in forced continuous

applications with low ripple current at light loads. If forced

3736fa

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