LTC3616 Datasheet, PDF (21/28 Pages) Linear Technology – 6A, 4MHz Monolithic Synchronous Step-Down DC/DC Converter

LTC3616
APPLICATIONS INFORMATION
For coincident start-up, the voltage value at the TRACK/SS
pin for the slave channel needs to reach the final reference
value after the internal soft-start time (around 1ms). The
master start-up time needs to be adjusted with an external
capacitor and resistor to ensure this.
External Reference Input (DDR Mode)
If the DDR pin is tied to SV_IN (DDR mode), the run state
is entered when V_TRACK/SS exceeds 0.3V and tracking
down behavior is possible if the V_TRACK/SS voltage is
below 0.6V.
This allows TRACK/SS to be used as an external reference
between 0.3V and 0.6V if desired. During the run state in
DDR mode, the power good window moves in relation
to the actual TRACK/SS pin voltage if the voltage value
is between 0.3V and 0.6V. Note: if TRACK/SS voltage is
0.6V, either the tracking circuit or the internal reference
can be used.
During up/down tracking the output current foldback is
disabled and the PGOOD pin is always pulled down (see
Figure 9).
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses: V_IN quiescent current and I²R losses. The V_IN
quiescent current loss dominates the efficiency loss at
very low load currents whereas the I²R loss dominates
the efficiency loss at medium to high load currents. In a
typical efficiency plot, the efficiency curve at very low load
currents can be misleading since the actual power lost is
usually of no consequence.
1. The V_IN quiescent current is due to two components: the
DC bias current as given in the Electrical Characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
low to high to low again, a packet of charge dQ moves
from V_IN to ground. The resulting dQ/dt is the current
out of V_IN due to gate charge, and it is typically larger
than the DC bias current. Both the DC bias and gate
charge losses are proportional to V_IN; thus, their effects
will be more pronounced at higher supply voltages.
2. I²R losses are calculated from the resistances of the
internal switches, R_SW, and external inductor, R_L. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R_DS(ON) and the duty cycle
(DC) as follows:
R_SW = (R_DS(ON)TOP)(DC) + (R_DS(ON)BOT)(1 – DC)
The R_DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Character-
istics curves. To obtain I²R losses, simply add R_SW to
R_L and multiply the result by the square of the average
output current.
Other losses including C_IN and C_OUT ESR dissipative
losses and inductor core losses generally account for
less than 2% of the total loss.
3616f
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