LTC3892_15 Datasheet, PDF (20/36 Pages) Linear Technology – 60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller

LTC3892/LTC3892-1
Applications Information
This formula has a maximum at V_IN = 2V_OUT, where I_RMS
= I_OUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3892/LTC3892-1, ceramic
capacitors can also be used for C_IN. Always consult the
manufacturer if there is any question.
The benefit of the LTC3892/LTC3892-1 2-phase opera-
tion can be calculated by using Equation 1 for the higher
power controller and then calculating the loss that would
have resulted if both controller channels switched on at
the same time. The total RMS power lost is lower when
both controllers are operating due to the reduced overlap
of current pulses required through the input capacitor’s
ESR. This is why the input capacitor’s requirement cal-
culated above for the worst-case controller is adequate
for the dual controller design. Also, the input protection
fuse resistance, battery resistance, and PC board trace
resistance losses are also reduced due to the reduced
peak currents in a 2-phase system. The overall benefit of
a multiphase design will only be fully realized when the
source impedance of the power supply/battery is included
in the efficiency testing. The drains of the top MOSFETs
should be placed within 1cm of each other and share a
common C_IN(s). Separating the drains and C_IN may pro-
duce undesirable voltage and current resonances at V_IN.
A small (0.1μF to 1μF) bypass capacitor between the chip
V_BIAS pin and ground, placed close to the LTC3892, is also
suggested. A 2.2Ω to 10Ω resistor placed between C_IN
(C1) and the V_BIAS pin provides further isolation.
The selection of C_OUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (∆V_OUT) is approximated by:
∆V_OUT
≈
∆I_L


ESR +
8
•
f
1
• C_OUT


where f is the operating frequency, C_OUT is the output
capacitance and ∆I_L is the ripple current in the inductor.
The output ripple is highest at maximum input voltage
since ∆I_L increases with input voltage.
Setting Output Voltage
The LTC3892/LTC3892-1 output voltages are set by an
external feedback resistor divider carefully placed across
the output, as shown in Figure 3a. The regulated output
voltage is determined by:
V_OUT
=
0.8V


1
+
R_B
R_A


To improve the frequency response, a feedforward ca-
pacitor, C_FF, may be used. Great care should be taken to
route the V_FB line away from noise sources, such as the
inductor or the SW line.
For the LTC3892, channel 1 has the option to be pro-
grammed to a fixed 5V or 3.3V output through control of
the VPRG1 pin (not available on the LTC3892-1). Figure 3b
shows how the V_FB1 pin is used to sense the output
voltage in fixed output mode. Tying VPRG1 to INTV_CC or
GND programs V_OUT1 to 5V or 3.3V, respectively. Float-
ing VPRG1 sets V_OUT1 to adjustable output mode using
external resistors.
V_OUT
1/2 LTC3892/
LTC3892-1
V_FB
R_B
C_FF
R_A
38921 F05a
(3a) Setting Adjustable Output Voltage
LTC3892
INTV_CC/GND VPRG1 V_FB1
V_OUT1
5V/3.3V
C_OUT
38921 F05b
(3b) Setting CH1 (LTC3892) to Fixed 5V/3.3V Voltage
Figure 3. Setting Buck Output Voltage
20
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38921f