LTC3892_15 Datasheet, PDF (19/36 Pages) Linear Technology – 60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller

LTC3892/LTC3892-1
Applications Information
voltage and maximum output current. Miller capacitance,
C_MILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. C_MILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in V_DS. This result is
then multiplied by the ratio of the application applied V_DS
to the gate charge curve specified V_DS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle = ^VOUT
V_IN
Synchronous Switch Duty Cycle = ^{VIN − VOUT}
V_IN
The MOSFET power dissipations at maximum output
current are given by:
( ) ^{( ) P}MAIN
=
V_OUT
V_IN
I_{OUT(MAX )}
2
1+ δ R_DS(ON) +
(V_IN
)²


I_{OUT(MAX )}
2


(R_DR
)(C_MILLER
)
•



V_DRVCC
1
− V_THMIN
+
1
V_THMIN
_(f)

( ) ^{( ) P}_SYNC
=
V_IN
− V_OUT
V_IN
I_{OUT(MAX )}
2
1+ δ
R_DS(ON)
where δ is the temperature dependency of R_DS(ON) and
R_DR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. V_THMIN is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I²R losses while the main N-channel
equations include an additional term for transition losses,
which are highest at high input voltages. For V_IN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for V_IN > 20V the transition losses rapidly
increase to the point that the use of a higher R_DS(ON) device
with lower C_MILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R_DS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
Optional Schottky diodes placed across the synchronous
MOSFET conduct during the dead-time between the con-
duction of the two power MOSFETs. This prevents the
body diode of the synchronous MOSFET from turning
on, storing charge during the dead-time and requiring a
reverse recovery period that could cost as much as 3%
in efficiency at high V_IN. A 1A to 3A Schottky is generally
a good compromise for both regions of operation due to
the relatively small average current. Larger diodes result
in additional transition losses due to their larger junction
capacitance.
C_IN and C_OUT Selection
The selection of C_IN is simplified by the 2-phase architec-
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can be
shown that the worst-case capacitor RMS current occurs
when only one controller is operating. The controller with
the highest (V_OUT)(I_OUT) product needs to be used in the
formula shown in Equation 1 to determine the maximum
RMS capacitor current requirement. Increasing the out-
put current drawn from the other controller will actually
decrease the input RMS ripple current from its maximum
value. The opt-of-phase technique typically reduces the
input capacitor’s RMS ripple current by a factor of 30%
to 70% when compared to a single phase power supply
solution.
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (V_OUT)/(V_IN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
( )( ) ^C_IN ^Required
I_RMS
≈
I_MAX
V_IN

V_OUT
V_IN − V_OUT ^1/2 ₍₁₎
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38921f
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