LTC3711 Datasheet, PDF (20/24 Pages) Linear Technology – 5-Bit Adjustable, Wide Operating Range, No RSENSE

LTC3711
APPLICATIO S I FOR ATIO
The corresponding change in the output voltage is deter-
mined by the gain of the error amplifier and feedback
divider. The LTC3711 error amplifier has a transconduc-
tance g_m that is constant over both temperature and a wide
± 40mV input range. Thus, by connecting a load resis-
tance R_VP to the I_TH pin, the error amplifier gain can be
precisely set for accurate active voltage positioning.
∆I_TH
=

g_m R_{VP }
0.8V
V_OUT


∆V_OUT
Solving for this resistance value:
R_VP
=
V_OUT ∆I_TH
(0.8V)g_m ∆V_OUT
= ^{(1.5V)(1.08V)} = 9.53k
(0.8V)(1.7mS)(125mV)
The gain setting resistance R_VP is implemented with two
resistors, R_VP1 connected from I_TH to ground and R_VP2
connected from I_TH to INTV_CC. The parallel combination of
these resistors must equal R_VP and their ratio determines
nominal value of the I_TH pin voltage when the error
amplifier input is zero. To center the load line around the
regulation point, the I_TH pin voltage must be set to corre-
spond to half the output current. The relation between I_TH
voltage and the output current is:
I_TH(NOM)
=


12V
V_RNG


^RSENSE^IOUT
–
1
2

∆I_{L }
+
0.8V
( ) ⁼


12V
0.5V


0.003Ω


7.5A
–
1
2

4.7A_
+ 0.8V
= 1.17V
The modified circuit is shown in Figure 10. Figures 11
and␣ 12 show the transient response without and with
active voltage positioning. Both circuits easily stay within
±100mV of the 1.5V output. However, the circuit with
active voltage positioning accomplishes this with only
three output capacitors rather than five. Refer to Design
Solutions 10 for additional information about active volt-
age positioning.
PC Board Layout Checklist
When laying out the printed circuit board, use the follow-
ing checklist to ensure proper operation of the controller.
These items are also illustrated in Figure 11.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to the
source of M2.
• Place M2 as close to the controller as possible, keeping
the PGND, BG and SENSE⁺ traces short.
• Connect the input capacitor(s) C_IN close to the power
MOSFETs. This capacitor carries the MOSFET AC
current.
• Keep the high dV/dT SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Connect the INTV_CC decoupling capacitor C_VCC closely
to the INTV_CC and PGND pins.
• Connect the top driver boost capacitor C_B closely to the
BOOST and SW pins.
• Connect the V_IN pin decoupling capacitor C_F closely to
the V_IN and PGND pins.
• VID0-VID4 interface circuitry must return to SGND.
Solving for the required values of the resistors:
R_VP1
=
5V
5V
– I_TH(NOM)
R_VP
=
5V
5V
– 1.17V
9.53k
= 12.44k
R_VP2
=
5V
I_TH(NOM)
R_VP
=
5V
1.17V
9.53k
=
40.73k
3711f
20