LTC3711 Datasheet, PDF (18/24 Pages) Linear Technology – 5-Bit Adjustable, Wide Operating Range, No RSENSE

LTC3711
APPLICATIO S I FOR ATIO
Figure 9 will provide adequate compensation for most
applications. For a detailed explanation of switching
control loop theory see Application Note 76.
Design Example
As a design example, take a supply with the following
specifications: V_IN = 7V to 24V (15V nominal), V_OUT = 1.5V
±100mV, I_OUT(MAX) = 15A, f = 300kHz. First, calculate the
timing resistor with V_ON = V_OUT:
( )( ) ^{RON =}
1
= 330k
300kHz 10pF
and choose the inductor for about 40% ripple current at
the maximum V_IN:
L
=
1.5V
(^300kHz)(^0.4)(^15A)
_1−
1.5V
24V

=
0.8µH
Selecting a standard value of 1µH results in a maximum
ripple current of:
( )( ) ^{∆IL =}
1.5V
300kHz 1µH

^1–
1.5V ^
24V 
=
4.7A
Next, choose the synchronous MOSFET switch. Because
of the narrow duty cycle and large current, a single SO-8
MOSFET will have difficulty dissipating the power lost in
the switch. Choosing two IRF7811A (R_DS(ON) = 0.013Ω,
C_RSS = 60pF, θ_JA = 50°C/W) yields a nominal sense voltage
of:
V_SNS(NOM) = (15A)(0.5)(1.3)(0.012Ω) = 117mV
Tying V_RNG to INTV_CC will set the current sense voltage
range for a nominal value of 140mV with current limit
occurring at 186mV. To check if the current limit is
acceptable, assume a junction temperature of about 100°C
above a 50°C ambient with ρ_150°C = 1.6:
( )( )( ) ^{( ) ILIMIT ≥}
0.5
186mV
1.6 0.012Ω
+¹
2
4.7A
= 18A
and double check the assumed T_J in the MOSFET:
18
( )( ) ^PBOT
=
24V – 1.5V ^ 21.7A^{ 2}
24V  2 
1.6
0.012Ω
= 2.12W
T_J = 50°C + (2.12W)(50°C/W) = 156°C
Because the top MOSFET is on for such a short time, a
single IRF7811A will be sufficient. Checking its power
dissipation at current limit with ρ_90°C = 1.3:
( ) ( )( ) ^PBOT
=
1.5V
24V
2
21.7A 1.3
0.012Ω
+
(^1.7)(^24V)²( )( )( ) ^{21.7A 60pF 300kHz}
= 0.46W + 0.38W = 0.84W
T_J = 50°C + (0.84W)(50°C/W) = 92°C
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
C_IN is chosen for an RMS current rating of about 6A at
temperature. The output capacitors are chosen for a low
ESR of 0.005Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
∆V_OUT(RIPPLE) = ∆I_L(MAX) (ESR)
= (4.7A) (0.005Ω) = 24mV
However, a 0A to 15A load step will cause an output
change of up to:
∆V_OUT(STEP) = ∆I_LOAD (ESR) = (15A) (0.005Ω) = 75mV
The complete circuit is shown in Figure 9.
Active Voltage Positioning
Active voltage positioning (also termed load “deregula-
tion” or droop) describes a technique where the output
voltage varies with load in a controlled manner. It is useful
in applications where rapid load steps are the main cause
of error in the output voltage. By positioning the output
voltage above the regulation point at zero load, and below
the regulation point at full load, one can use more of the
error budget for the load step. This allows one to reduce
the number of output capacitors by relaxing the ESR
requirement.
3711f