LTC3615-1_15 Datasheet, PDF (20/32 Pages) Linear Technology – Dual 4MHz, 3A Synchronous Step-Down DC/DC Converter

LTC3615/LTC3615-1
Applications Information
Applications section uses faster compensation to improve
load step response.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C_OUT, causing a rapid drop in V_OUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. More output
capacitance may be required depending on the duty cycle
and load step requirements.
If the ITH pin is tied to SV_IN, the active voltage positioning
(AVP) mode and the internal compensation is selected.
In AVP mode, the load regulation performance is inten-
tionally reduced, setting the output voltage at a point that
is dependent on the load current. When the load current
suddenly increases, the output voltage starts from a level
slightly higher than nominal so the output voltage can
droop more and stay within the specified voltage range.
When the load current suddenly decreases, the output
voltage starts at a level lower than nominal so the output
voltage can have more overshoot and stay within the
specified voltage range. This behavior is demonstrated
in Figure 6.
The benefit is a lower peak-to-peak output voltage deviation
for a given load step without having to increase the output
filter capacitance. Alternatively, the output voltage filter
capacitance can be reduced while maintaining the same
peak-to-peak transient response. For this operation mode,
the loop gain is reduced and no external compensation
is required.
Programmable Switch Pin Slew Rate
As switching frequencies rise, it is desirable to minimize the
transition time required when switching to minimize power
losses and blanking time for the switch to settle. However,
fast slewing of the switch node results in relatively high
external radiated EMI and high on-chip supply transients,
which can cause problems for some applications.
V_OUT
200mV/DIV
3A
I_L
1A/DIV
100mA
50µs/DIV
3615 F05
V_OUT = 1.8V
I_LOAD = 100mA TO 3A
V_MODE = 1.5V
COMPENSATION AND OUTPUT CAPACITOR
VALUES OF FIGURE 3
Figure 5. Load Step Transient in FCM with External Compensation
V_OUT
100mV/DIV
I_L
1A/DIV
50µs/DIV
V_OUT = 1.8V
I_LOAD = 100mA TO 3A
V_MODE = 1.5V
V_IN = V_ITH = 3.3V
OUTPUT CAPACITOR VALUE FIGURE 3
3615 F06
Figure 6. Load Step Transient in FCM in AVP Mode
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