LTC3615-1_15 Datasheet, PDF (16/32 Pages) Linear Technology – Dual 4MHz, 3A Synchronous Step-Down DC/DC Converter

LTC3615/LTC3615-1
Applications Information
V_{IN LTC3615}
SV_IN
R_T/SYNC
f_SW
2.25MHz
V_{IN LTC3615}
0.4V
SV_IN
R_T/SYNC
R_OSC
SGND
f_SW ∝1/R_OSC
V_{IN LTC3615}
SV_IN
f_SW
R_T/SYNC ^1/TP
1.2V SGND
0.3V
T_P
15pF
T_P
1.2V
0.3V
V_{IN LTC3615}
SV_IN
f_SW
R_T/SYNC ^1/TP
R_T
SGND
3615 F04
Figure 4. Setting the Switching Frequency
of periods to settle until the frequency at SW matches the
frequency and phase of R_T/SYNC.
When the external clock signal is removed, the LTC3615
needs approximately 5µs to detect the absence of the
external clock. During this time, the PLL will continue to
provide clock cycles before it is switched back to the de-
fault frequency or selected frequency (set via the external
R_T resistor).
A safe way of driving the R_T/SYNC input is with an AC
coupling to the clock generator via a 15pF capacitor. The
AC coupling avoids complications if the external clock
generator cannot provide a continuous clock signal at the
time of start-up, operation and shut down of the LTC3615.
In general, any abrupt clock frequency change of the
regulator will have an effect on the SW pin timing and
may cause equally sudden output voltage changes. This
must be taken into account in particular if the external
clock frequency is significantly different from the internal
default of 2.25MHz.
Phase Selection
Channel 2 of the LTC3615 will operate in-phase, 180°
out-of-phase (anti-phase) or shifted by 90° from chan-
nel 1 depending on the state of the PHASE pin—low,
midrail and high, respectively. Channel 2 of LTC3615-1
will operate 180° out-of-phase (anti-phase) with PHASE
pin high or shifted by 140° with PHASE midrail or low.
Antiphase generally reduces input voltage and current
ripple. Crosstalk between switch nodes SW1, SW2 and
components or sensitive lines connected to FBx, ITHx, R_T/
SYNC or SRLIM can cause unstable switching waveforms
and unexpectedly large input and output voltage ripple.
on the duty cycle of the two channels, choose the phase
difference between the channels to keep edges as far away
from each other as possible.
For example, for duty cycles of less than 40% for one
channel and more than 60% for the other channel, the
SW node edges will not coincide for 0° or 180° phase
shifts. If both channels have a duty cycle of around 50%,
a 90° phase difference would be a better choice. In cases
where the duty cycles are ~25% and ~50%, a 140° phase
shift (LTC3615-1 only) is preferable to the other phase
selections.
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ∆I_L increases with higher V_IN and decreases
with higher inductance.
ΔI_L
=
⎛
⎜
⎝
V_OUT
f_SW • L
⎞
⎟
⎠
⎛
• _{⎝⎜⎜}1–
V_OUT
V_IN(MAX
)
⎞
⎠⎟⎟
Having a lower ripple current reduces the core losses
in the inductor, the ESR losses in the output capacitors
and the output voltage ripple. A reasonable starting point
for selecting the ripple current is ∆I_L = 0.3(I_OUT(MAX)).
The largest ripple current occurs at the highest V_IN. To
guarantee that the ripple current stays below a specified
maximum, the inductor value should be chosen according
to the following equation:
L
=
⎛
⎝⎜⎜
f_SW
V_OUT
• ΔI_L(MAX
)
⎞
⎠⎟⎟
•
⎛
⎝⎜⎜^1–
V_OUT
V_{IN (MAX )}
⎞
⎠⎟⎟
The situation improves if rising and falling edges of the _{The inductor value will also have an effect on Burst Mode}
switch nodes are timed carefully not to coincide. Depending _{operation. The transition to low current operation begins}
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