LTC3857-1_15 Datasheet, PDF (19/38 Pages) Linear Technology – Low IQ, Dual, 2-Phase Synchronous Step-Down Controller

LTC3857-1
APPLICATIONS INFORMATION
RMS capacitor current requirement. Increasing the out-
put current drawn from the other controller will actually
decrease the input RMS ripple current from its maximum
value. The out-of-phase technique typically reduces the
input capacitor’s RMS ripple current by a factor of 30%
to 70% when compared to a single phase power supply
solution.
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (V_OUT)/(V_IN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
C_IN
Required I_RMS
≈
I_MAX
V_IN
⎡⎣(V_OUT )(V_IN
–
) V_OUT ⎤⎦^1/2
(1)
This formula has a maximum at V_IN = 2V_OUT, where I_RMS
= I_OUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3857-1, ceramic capacitors
can also be used for C_IN. Always consult the manufacturer
if there is any question.
The benefit of the LTC3857-1 2-phase operation can be
calculated by using Equation 1 for the higher power control-
ler and then calculating the loss that would have resulted
if both controller channels switched on at the same time.
The total RMS power lost is lower when both controllers
are operating due to the reduced overlap of current pulses
required through the input capacitor’s ESR. This is why
the input capacitor’s requirement calculated above for the
worst-case controller is adequate for the dual controller
design. Also, the input protection fuse resistance, battery
resistance, and PC board trace resistance losses are also
reduced due to the reduced peak currents in a 2-phase
system. The overall benefit of a multiphase design will
only be fully realized when the source impedance of the
power supply/battery is included in the efficiency testing.
The drains of the top MOSFETs should be placed within
1cm of each other and share a common C_IN(s). Separating
the drains and C_IN may produce undesirable voltage and
current resonances at V_IN.
A small (0.1μF to 1μF) bypass capacitor between the chip
V_IN pin and ground, placed close to the LTC3857-1, is
also suggested. A 10Ω resistor placed between C_IN (C1)
and the V_IN pin provides further isolation between the
two channels.
The selection of C_OUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (ΔV_OUT) is approximated by:
ΔV_OUT
≈
ΔI_L
⎛
⎝⎜
ESR
+
8
•
f
1
• C_OUT
⎞
⎠⎟
where f is the operating frequency, C_OUT is the output
capacitance and ΔI_L is the ripple current in the inductor.
The output ripple is highest at maximum input voltage
since ΔI_L increases with input voltage.
Setting Output Voltage
The LTC3857-1 output voltages are each set by an exter-
nal feedback resistor divider carefully placed across the
output, as shown in Figure 5. The regulated output voltage
is determined by:
V_OUT
=
0.8V
⎛
⎝⎜
1+
R_B
R_A
⎞
⎠⎟
To improve the frequency response, a feedforward ca-
pacitor, C_FF, may be used. Great care should be taken to
route the V_FB line away from noise sources, such as the
inductor or the SW line.
V_OUT
1/2 LTC3857-1
V_FB
R_B
C_FF
R_A
38571 F05
Figure 5. Setting Output Voltage
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