LTC3633A-1_15 Datasheet, PDF (19/30 Pages) Linear Technology – Dual Channel 3A, 20V Monolithic Synchronous Step-Down Regulator

LTC3633A/LTC3633A-1
APPLICATIONS INFORMATION
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
% Efficiency = 100% – (L1 + L2 + L3 +…)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, three main sources usually account for most of
the losses in LTC3633A circuits: 1) I²R losses, 2) switch-
ing losses and quiescent power loss 3) transition losses
and other losses.
1. I²R losses are calculated from the DC resistances of
the internal switches, R_SW, and external inductor, R_L.
In continuous mode, the average output current flows
through inductor L but is “chopped” between the
internal top and bottom power MOSFETs. Thus, the
series resistance looking into the SW pin is a function
of both top and bottom MOSFET R_DS(ON) and the duty
cycle (DC) as follows:
R_SW = (R_DS(ON)TOP)(DC) + (R_DS(ON)BOT)(1 – DC)
The R_DS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus to obtain I²R losses:
I²R losses = I_OUT2(R_SW + R_L)
2. The internal LDO supplies the power to the INTV_CC rail.
The total power loss here is the sum of the switching
losses and quiescent current losses from the control
circuitry.
Each time a power MOSFET gate is switched from low
to high to low again, a packet of charge dQ moves from
V_IN to ground. The resulting dQ/dt is a current out of
INTV_CC that is typically much larger than the DC control
bias current. In continuous mode, I_GATECHG = f(Q_T + Q_B),
where Q_T and Q_B are the gate charges of the internal
top and bottom power MOSFETs and f is the switching
frequency. For estimation purposes, (Q_T + Q_B) on each
LTC3633A regulator channel is approximately 2.3nC.
To calculate the total power loss from the LDO load,
simply add the gate charge current and quiescent cur-
rent and multiply by V_IN:
P_LDO = (I_GATECHG + I_Q) • V_IN
3. Other “hidden” losses such as transition loss, cop-
per trace resistances, and internal load currents can
account for additional efficiency degradations in the
overall power system. Transition loss arises from the
brief amount of time the top power MOSFET spends
in the saturated region during switch node transitions.
The LTC3633A internal power devices switch quickly
enough that these losses are not significant compared
to other sources.
Other losses, including diode conduction losses during
dead-time and inductor core losses, generally account
for less than 2% total additional loss.
Thermal Considerations
The LTC3633A requires the exposed package backplane
metal (PGND) to be well soldered to the PC board to
provide good thermal contact. This gives the QFN and
TSSOP packages exceptional thermal properties, which
are necessary to prevent excessive self-heating of the part
in normal operation.
In a majority of applications, the LTC3633A does not dis-
sipate much heat due to its high efficiency and low thermal
resistance of its exposed-back QFN package. However, in
applications where the LTC3633A is running at high ambi-
ent temperature, high V_IN, high switching frequency, and
maximum output current load, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will be turned off until temperature
returns to 140°C.
To prevent the LTC3633A from exceeding the maximum
junction temperature of 125°C, the user will need to do
some thermal analysis. The goal of the thermal analysis
For more information www.linear.com/LTC3633A
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