LTC3633A-1_15 Datasheet, PDF (16/30 Pages) Linear Technology – Dual Channel 3A, 20V Monolithic Synchronous Step-Down Regulator

LTC3633A/LTC3633A-1
APPLICATIONS INFORMATION
Internal/External Loop Compensation
The LTC3633A provides the option to use a fixed internal
loop compensation network to reduce both the required
external component count and design time. The internal
loop compensation network can be selected by connect-
ing the ITH pin to the INTV_CC pin. To ensure stability it is
recommended that internal compensation only be used with
applications with f_SW > 1MHz. Alternatively, the user may
choose specific external loop compensation components
to optimize the main control loop transient response as
desired. External loop compensation is chosen by simply
connecting the desired network to the ITH pin.
Suggested compensation component values are shown in
Figure 3. For a 2MHz application, an R-C network of 220pF
and 13kΩ provides a good starting point. The bandwidth
of the loop increases with decreasing C. If R is increased
by the same factor that C is decreased, the zero frequency
will be kept the same, thereby keeping the phase the same
in the most critical frequency range of the feedback loop.
A 10pF bypass capacitor on the ITH pin is recommended
for the purposes of filtering out high frequency coupling
from stray board capacitance. In addition, a feedforward
capacitor C_F can be added to improve the high frequency
response, as previously shown in Figure 2. Capacitor C_F
provides phase lead by creating a high frequency zero
with R2 which improves the phase margin.
ITH
LTC3633A
SGND
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R_COMP
13k
C_COMP
220pF
Figure 3. Compensation Component
Checking Transient Response
The regulator loop response can be checked by observing
the response of the system to a load step. When configured
for external compensation, the availability of the ITH pin
not only allows optimization of the control loop behavior
but also provides a DC-coupled and AC filtered closed loop
response test point. The DC step, rise time, and settling
behavior at this test point reflect the closed loop response.
Assuming a predominantly second order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin.
The ITH external components shown in Figure 3 circuit
will provide an adequate starting point for most applica-
tions. The series R-C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because their various types and values determine the
loop gain and phase. An output current pulse of 20% to
100% of full load current having a rise time of ~1µs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V_OUT im-
mediately shifts by an amount equal to ΔI_LOAD • ESR, where
ESR is the effective series resistance of C_OUT. ΔI_LOAD also
begins to charge or discharge C_OUT generating a feedback
error signal used by the regulator to return V_OUT to its
steady-state value. During this recovery time, V_OUT can
be monitored for overshoot or ringing that would indicate
a stability problem.
When observing the response of V_OUT to a load step, the
initial output voltage step may not be within the bandwidth
of the feedback loop, so the standard second order over-
shoot/DC ratio cannot be used to determine phase margin.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
In some applications, a more severe transient can be caused
by switching in loads with large (>10µF) input capacitors.
The discharged input capacitors are effectively put in paral-
lel with C_OUT, causing a rapid drop in V_OUT. No regulator
can deliver enough current to prevent this problem, if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the load
switch driver. A hot swap controller is designed specifically
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