LTC3445_15 Datasheet, PDF (19/24 Pages) Linear Technology – I2C Controllable Buck Regulator with Two LDOs

LTC3445
APPLICATIO S I FOR ATIO
1000
100
10
DAC MAX
DAC MIN
1
0.1
0.1
1
10
100
LOAD CURRENT (mA)
1000
3445 F08
Figure 8. Power Loss vs Load Current, V_CC1 = 3.6V
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge, dQ, moves from V_CC1 to ground. The resulting
dQ/dt is the current out of V_CC1 that is typically larger
than the DC bias current. In continuous mode, I_GATECHG
= f(Q_T + Q_B) where Q_T and Q_B are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to V_CC1 and thus
their effects will be more pronounced at higher supply
voltages.
2. I²R losses are calculated from the resistances of the
internal switches, R_SW, and external inductor R_L. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R_DS(ON) and the duty cycle
(DC) as follows:
R_SW = (R_DS(ON)TOP)(DC) + (R_DS(ON)BOT)(1 – DC)
The R_DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Charateristics
curves. Thus, to obtain I²R losses, simply add R_SW to
R_L and multiply the result by the square of the average
output current.
Other losses including C_IN and C_OUT ESR dissipative
losses and inductor core losses generally account for
less than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V_OUT immediately shifts by an amount
equal to (∆I_LOAD • ESR), where ESR is the effective series
resistance of C_OUT. ∆I_LOAD also begins to charge or
discharge C_OUT, which generates a feedback error signal.
The regulator loop then acts to return V_OUT to its steady-
state value. During this recovery time V_OUT can be moni-
tored for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C_OUT, causing a rapid drop in V_OUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • C_LOAD).
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.
LDO REGULATORS
The LDOs in the LTC3445 are 50mA low dropout regula-
tors with low quiescent and shutdown currents. Each
device is capable of supplying 50mA at a dropout voltage
of 300mV. The LDOs are current limited to greater than
50mA but less than 75mA. The output voltages of the
LDOs are set with external resistive dividers according to
the following formula:
V_LDOOUT1 = 0.6(1 + R1/R2)
(4)
V_LDOOUT2 = 0.6(1 + R3/R4)
(5)
Output Capacitance and Transient Response
The LTC3445 LDOs are designed to be stable with a wide
range of output capacitors. A minimum output capacitor
of 2.2µF with an ESR of 3Ω or less is recommended to
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