LTC3445_15 Datasheet, PDF (15/24 Pages) Linear Technology – I2C Controllable Buck Regulator with Two LDOs

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OPERATIO (refer to Figure 1)
be able to control the data line to acknowledge communi-
cations from the master, and some devices will need to
able to send data back to the master; they will be in control
of the data line while they are doing so. Many slave devices
will have no need to stretch the clock signal and will have
no ability to pull the clock line low, which is the case with
the LTC3445.
Data is exchanged in the form of bytes, which are 8-bit
packets. Any byte needs to be acknowledged by the slave
(data line pulled low) or not acknowledged by the master
(data line left high), so communications are broken up into
9-bit segments, one byte followed by one bit for acknowl-
edging. For example, sending out an address consists of
7 bits of device address, 1 bit that signals whether a read
or write operation will be performed, and then 1 more bit
to allow the slave to acknowledge. There is no theoretical
limit to how many total bytes can be exchanged in a given
transmission.
I²C and SMBus are very similar specifications, SMBus
having been derived from I²C. In general, SMBus is
targeted to low power devices (particularly battery-pow-
ered ones) and emphasizes low power consumption,
while I²C is targeted to higher speed systems where the
power consumption of the bus is not so critical. I²C has
three different specifications for three different maximum
speeds, these being standard mode (100kHz max), fast
mode (400kHz max) and HS mode (3.4MHz max). Stan-
dard and fast mode are not radically different, but HS mode
is very different from a hardware and software perspective
and requires an initiating command at standard or fast
speed before data can start transferring at HS speed.
SMBus simply specifies a 100kHz maximum speed.
LTC3445
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a transmission
with a START condition by transitioning SDA from high to
low while SCL is high. When the master has finished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. An acknowledge signal (LOW
active) as generated by the slave lets the master know that
the latest byte of information was received. The acknowl-
edge-related clock pulse is generated by the master. The
transmitter master releases the SDA line (HIGH) during
the acknowledge clock pulse. The slave receiver must pull
down the SDA line during the acknowledge clock pulse so
that it remains stable LOW during the HIGH period of this
clock pulse.
When a slave receiver doesn’t acknowledge the slave
address (for example, it’s unable to receive because it’s
performing some real-time function), the data line must be
left HIGH by the slave. The master can then generate a
STOP condition to abort the transfer.
If a slave receiver does acknowledge the slave address but,
some time later in the transfer cannot receive any more
data bytes, the master must again abort the transfer. This
is indicated by the slave generating the not acknowledge
on the first byte to follow. The slave leaves the data line
HIGH and the master generates the STOP condition. The
WRITE BYTE PROTOCOL
1
7
1
START AA01011 WR
SLAVE
ADDRESS ₀
1
ACK
S
0
8
1
XXXXXAAA ACK
REGISTER S
ADDRESS ₀
8
1
DDDDDDDD ACK
DATA S
BYTE
0
1
STOP
READ BYTE PROTOCOL
1
7
1
START AA01011 WR
SLAVE
ADDRESS ₀
1
8
1
ACK XXXXXAAA ACK
S
REGISTER S
0
ADDRESS ₀
1
7
1
START AA01011 RD
SLAVE
ADDRESS ₁
1
ACK
S
0
8
1
1
DDDDDDDD ACK STOP
DATA M
BYTE
1
3445 G07
Figure 7
3445fa
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