LTC4007_1 Datasheet, PDF (16/24 Pages) Linear Technology – 4A, High Efficiency, Standalone Li-Ion Battery Charger

LTC4007
APPLICATIO S I FOR ATIO
Charger Switching Power MOSFET
and Diode Selection
Two external power MOSFETs must be selected for use
with the charger: a P-channel MOSFET for the top (main)
switch and an N-channel MOSFET for the bottom (syn-
chronous) switch.
The peak-to-peak gate drive levels are set internally. This
voltage is typically 6V. Consequently, logic-level threshold
MOSFETs must be used. Pay close attention to the BV_DSS
specification for the MOSFETs as well; many of the logic
level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON”
resistance R_DS(ON), total gate capacitance QG, reverse
transfer capacitance C_RSS, input voltage and maximum
output current. The charger is operating in continuous
mode at moderate to high currents so the duty cycles for
the top and bottom MOSFETs are given by:
Main Switch Duty Cycle = V_OUT/V_IN
Synchronous Switch Duty Cycle = (V_IN – V_OUT)/V_IN.
The MOSFET power dissipations at maximum output
current are given by:
PMAIN = V_OUT/V_IN(I_MAX)²(1 + δ∆T)R_DS(ON)
+ k(V_IN)²(I_MAX)(C_RSS)(f_OSC)
PSYNC = (V_IN – V_OUT)/V_IN(I_MAX)²(1 + δ∆T)R_DS(ON)
Where δ∆T is the temperature dependency of R_DS(ON) and
k is a constant inversely related to the gate drive current.
Both MOSFETs have I²R losses while the PMAIN equation
includes an additional term for transition losses, which are
highest at high input voltages. For V_IN < 20V the high
current efficiency generally improves with larger MOS-
FETs, while for V_IN > 20V the transition losses rapidly
increase to the point that the use of a higher R_DS(ON) device
with lower C_RSS actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage or during a short circuit when the duty cycle in this
switch in nearly 100%. The term (1 + δ∆T) is generally
given for a MOSFET in the form of a normalized R_DS(ON) vs
temperature curve, but δ = 0.005/°C can be used as an
approximation for low voltage MOSFETs. C_RSS = Q_GD/∆V_DS
is usually specified in the MOSFET characteristics. The
constant k = 2 can be used to estimate the contributions of
the two terms in the main switch dissipation equation.
If the charger is to operate in low dropout mode or with a
high duty cycle greater than 85%, then the topside
P-channel efficiency generally improves with a larger
MOSFET. Using asymmetrical MOSFETs may achieve cost
savings or efficiency gains.
The Schottky diode D1, shown in the Typical Application
on the back page, conducts during the dead-time between
the conduction of the two power MOSFETs. This prevents
the body diode of the bottom MOSFET from turning on and
storing charge during the dead-time, which could cost as
much as 1% in efficiency. A 1A Schottky is generally a
good size for 4A regulators due to the relatively small
average current. Larger diodes can result in additional
transition losses due to their larger junction capacitance.
The diode may be omitted if the efficiency loss can be
tolerated.
Calculating IC Power Dissipation
The power dissipation of the LTC4007 is dependent upon
the gate charge of the top and bottom MOSFETs (QG1 &
QG2 respectively) The gate charge is determined from the
manufacturer’s data sheet and is dependent upon both the
gate voltage swing and the drain voltage swing of the
MOSFET. Use 6V for the gate voltage swing and V_DCIN for
the drain voltage swing.
PD = V_DCIN • (f_OSC (QG1 + QG2) + I_Q)
Example:
V_DCIN = 19V, f_OSC = 345kHz, QG1 = QG2 = 15nC,
I_Q = 5mA
PD = 292mW
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