LTC3785 Datasheet, PDF (16/20 Pages) Linear Technology – 10V, High Effi ciency, Synchronous, No RSENSE Buck-Boost Controller

LTC3785
APPLICATIO S I FOR ATIO
The maximum power dissipation of switch A and C oc-
curs in boost mode. Assuming a junction temperature
of T_J = 100°C with ρ_100C = 1.3, the power dissipation at
V_IN = 2.7, and using the equations from the Efficiency
Considerations section:
PA(BOOST) =
⎛
⎝⎜
3.3
2.7
⎞²
• 3_⎠⎟
•
1.3 • 0.025 =
0.43W
( ) PC(BOOST) = 3.3 – 2.7 • 3.3 • 32 • 1.3 • 0.025
2.7²
+ 1• 3.3³ • ³ • 0.45 – 9 • 500 • 10³
2.7
= 0.09W
The maximum power dissipation of switch B and D occurs
in buck mode and is given by:
PB(BUCK) = ^{10 – 3.3} • 3² • 1.3 • 0.025 = 0.20W
10
PD(BOOST) = ^3.3 • 3² • 1.3 • 0.025 = 0.10W
10
Now to double check the T_J of the package with 50°C
ambient. Since this is a dual NMOS package we can add
switches A + B and C + D worst case. For applications
where the MOSFETs are in separate packages each device’s
maximum T_J would have to be calculated.
T_J(PKG1) = T_A + θ_JA(PA + PB)
= 50 + 60 • (0.43 + 0.20) = 88°C
T_J(PKG2) = T_A + θ_JA(PC + PD)
= 50 + 60 • (0.09 + 0.10) = 60°C
Set The Maximum Current Limit
The equation for setting the maximum current limit of the
IC is given by:
R_ILSET
=
6e3
R_DS(ON)A • I_LIMIT
Ω
The maximum current is set 25% above I_L(PEAK) to account
for worst-case variation at 100°C = 6A.
R_ILSET
=
6e3
0.025 •
6
=
42k
Choose the Input and Output Capacitance
The input capacitance should filter current ripple which is
worst case in buck mode. Since the input current could
reach 6A, a capacitor ESR of 10mΩ or less will yield an
input ripple of 60mV.
The output capacitance should filter current ripple which
is worst in boost mode, but is usually dictated by the loop
response, the maximum load transient and the allowable
transient response.
PC BOARD LAYOUT CHECKLIST
The basic PC board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board
provides heat sinking for power components.
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
• Place C_IN, switch A, switch B and D1 in one compact
area. Place C_OUT, switch C, switch D and D2 in one
compact area.
• Use immediate vias to connect the components (includ-
ing the LTC3785’s GND/PGND pin) to the ground plane.
Use several large vias for each power component.
• Use planes for V_IN and V_OUT to maintain good voltage
filtering and to keep power losses low.
• Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. Connect the copper areas to any DC net
(V_IN or GND). When laying out the printed circuit board,
the following checklist should be used to ensure proper
operation of the LTC3785.
3785f
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