LTC3707 Datasheet, PDF (16/32 Pages) Linear Technology – High Effi ciency, 2-Phase Synchronous Step-Down Switching Regulator

LTC3707
APPLICATIONS INFORMATION
30% to 70% when compared to a single phase power
supply solution.
The type of input capacitor, value and ESR rating have
efficiency effects that need to be considered in the selec-
tion process. The capacitance value chosen should be
sufficient to store adequate charge to keep high peak
battery currents down. 20μF to 40μF is usually sufficient
for a 25W output supply operating at 200kHz. The ESR of
the capacitor is important for capacitor power dissipation
as well as overall battery efficiency. All of the power (RMS
ripple current • ESR) not only heats up the capacitor but
wastes power from the battery.
Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used
as input capacitors, but each has drawbacks: ceramic
voltage coefficients are very high and may have audible
piezoelectric effects; tantalums need to be surge-rated;
OS-CONs suffer from higher inductance, larger case size
and limited surface-mount applicability; electrolytics’
higher ESR and dryout possibility require several to be
used. Multiphase systems allow the lowest amount of
capacitance overall. As little as one 22μF or two to three
10μF ceramic capacitors are an ideal choice in a 20W to
50W power supply due to their extremely low ESR. Even
though the capacitance at 20V is substantially below their
rating at zero-bias, very low ESR loss makes ceramics
an ideal candidate for highest efficiency battery operated
systems. Also consider parallel ceramic and high quality
electrolytic capacitors as an effective means of achieving
ESR and bulk capacitance goals.
In continuous mode, the source current of the top N-channel
MOSFET is a square wave of duty cycle V_OUT/V_IN. To prevent
large voltage transients, a low ESR input capacitor sized for
the maximum RMS current of one channel must be used.
The maximum RMS capacitor current is given by:
( ) _{CIN RequiredIRMS ≈IMAX} ^{⎡⎣V}_OUT
V_IN − V_OUT
V_IN
⎤⎦^1/2
This formula has a maximum at V_IN = 2V_OUT, where
I_RMS = I_OUT/2. This simple worst case condition is com-
monly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturer’s
16
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the capaci-
tor, or to choose a capacitor rated at a higher temperature
than required. Several capacitors may also be paralleled
to meet size or height requirements in the design. Always
consult the manufacturer if there is any question.
The benefit of the LTC3707 multiphase can be calculated by
using the equation above for the higher power controller
and then calculating the loss that would have resulted if
both controller channels switch on at the same time. The
total RMS power lost is lower when both controllers are
operating due to the interleaving of current pulses through
the input capacitor’s ESR. This is why the input capacitor’s
requirement calculated above for the worst-case controller
is adequate for the dual controller design. Remember that
input protection fuse resistance, battery resistance and PC
board trace resistance losses are also reduced due to the
reduced peak currents in a multiphase system. The overall
benefit of a multiphase design will only be fully realized
when the source impedance of the power supply/battery
is included in the efficiency testing. The drains of the
two top MOSFETS should be placed within 1cm of each
other and share a common C_IN(s). Separating the drains
and C_IN may produce undesirable voltage and current
resonances at V_IN.
The selection of C_OUT is driven by the required effective
series resistance (ESR). Typically once the ESR require-
ment is satisfied the capacitance is adequate for filtering.
The output ripple (ΔV_OUT) is determined by:
ΔV_OUT
≈
ΔI_L
⎛
⎝⎜
ESR
+
1
8fC_OUT
⎞
⎠⎟
Where f = operating frequency, C_OUT = output capacitance,
and ΔI_L= ripple current in the inductor. The output ripple is
highest at maximum input voltage since ΔI_L increases with
input voltage. With ΔI_L = 0.3I_OUT(MAX) the output ripple will
typically be less than 50mV at max V_IN assuming:
C_OUT Recommended ESR < 2 R_SENSE
and C_OUT > 1/(8fR_SENSE)
The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guarantees
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