LTC3707 Datasheet, PDF (15/32 Pages) Linear Technology – High Effi ciency, 2-Phase Synchronous Step-Down Switching Regulator

LTC3707
APPLICATIONS INFORMATION
However, designs for surface mount are available that do
not increase the height significantly.
Power MOSFET and D1 Selection
Two external power MOSFETs must be selected for each
controller with the LTC3707: One N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTV_CC
voltage. This voltage is typically 5V during start-up
(see EXTV_CC Pin Connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected
(V_IN < 5V); then, sub-logic level threshold MOSFETs
(V_GS(TH) < 3V) should be used. Pay close attention to the
BV_DSS specification for the MOSFETs as well; most of the
logic level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON”
resistance R_DS(ON), reverse transfer capacitance C_RSS, input
voltage and maximum output current. When the LTC3707
is operating in continuous mode the duty cycles for the
top and bottom MOSFETs are given by:
Main Switch Duty Cycle = ^VOUT
V_IN
Synchronous Switch Duty Cycle = ^{VIN – VOUT}
V_IN
The MOSFET power dissipations at maximum output
current are given by:
( ) ( ) P_MAIN
=
V_OUT
V_IN
I_MAX
2
1+ δ
R_DS(ON) +
k(V_IN)² (I_MAX )₍C_{RSS )}(f)
( ) ( ) P_SYNC
=
V_IN
– V_OUT
V_IN
I_MAX
2
1+ δ
R_DS(ON)
where δ is the temperature dependency of R_DS(ON) and k
is a constant inversely related to the gate drive current.
Both MOSFETs have I²R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For V_IN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for V_IN > 20V the transition losses rapidly
increase to the point that the use of a higher R_DS(ON) device
with lower C_RSS actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1+δ) is generally given for a MOSFET in the
form of a normalized R_DS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. C_RSS is usually specified in the MOSFET
characteristics. The constant k = 1.7 can be used to esti-
mate the contributions of the two terms in the main switch
dissipation equation.
The Schottky diode D1 shown in Figure 1 conducts dur-
ing the dead-time between the conduction of the two
power MOSFETs. This prevents the body diode of the
bottom MOSFET from turning on, storing charge during
the dead-time and requiring a reverse recovery period
that could cost as much as 3% in efficiency at high V_IN.
A 1A to 3A Schottky is generally a good compromise for
both regions of operation due to the relatively small aver-
age current. Larger diodes result in additional transition
losses due to their larger junction capacitance. Schottky
diodes should be placed in parallel with the synchronous
MOSFETs when operating in pulse-skip mode or in Burst
Mode operation.
C_IN and C_OUT Selection
The selection of C_IN is simplified by the multiphase ar-
chitecture and its impact on the worst-case RMS current
drawn through the input network (battery/fuse/capacitor).
It can be shown that the worst case RMS current occurs
when only one controller is operating. The controller with
the highest (V_OUT)(I_OUT) product needs to be used in the
formula below to determine the maximum RMS current
requirement. Increasing the output current, drawn from
the other out-of-phase controller, will actually decrease the
input RMS ripple current from this maximum value (see
Figure 4). The out-of-phase technique typically reduces
the input capacitor’s RMS ripple current by a factor of
3707fb
15