LTC3548A Datasheet, PDF (15/20 Pages) Linear Technology – Dual Synchronous 400mA/800mA, 2.25MHz Step-Down DC/DC Regulator

LTC3548A
APPLICATIONS INFORMATION
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3548A. These items are also illustrated graphically
in the layout diagram of Figure 2. Check the following in
your layout:
1. Does the capacitor C_IN connect to the power V_IN (Pin 3)
and GND (Exposed Pad) as closely as possible? This
capacitor provides the AC current to the internal power
MOSFETs and their drivers.
2. Are C_OUT and L1 closely connected? The (–) plate of
C_OUT returns current to GND and the (–) plate of C_IN.
3. The resistor divider formed by R1 and R2 must be
connected between the (+) plate of C_OUT and a ground
sense line terminated near GND (Exposed Pad). The
feedback signals V_FB1 and V_FB2 should be routed away
from noisy components and traces, such as the SW lines
(Pins 4 and 7), and their traces should be minimized.
4. Keep sensitive components away from the SW pins.
The input capacitor, C_IN, and the resistors R1 to R4
should be routed away from the SW traces and the
inductors.
5. A ground plane is preferred, but if not available keep
the signal and power grounds segregated with small-
signal components returning to the GND pin at one
point. Additionally the two grounds should not share
the high current paths of C_IN or C_OUT.
6. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to V_IN or GND.
V_IN
V_OUT2
C5
R4
C_OUT2
C_IN
RUN/SS2 V_IN RUN/SS1
L2
MODE/SYNC
POR
SW2
SW1
LTC3548A
V_FB2
V_FB1
GND
R3
L1
C4
R2
R1
V_OUT1
C_OUT1
BOLD LINES INDICATE HIGH CURRENT PATHS
3548A F02
Figure 2. LTC3548A Layout Diagram (See Board Layout Checklist)
3548af
15